公开(公告)号：US10896680B2

公开(公告)日：2021-01-19

申请号：US16399671

申请日：2019-04-30

Applicant: AVNERA CORPORATION

Inventor： Christopher James O'Connor

IPC: G10L15/22 ,  G06N3/04 ,  G06F17/16 ,  G10L15/16 ,  G06F17/14 ,  H04R1/10 ,  G10L15/08

Abstract: A system for operating a headphone can include a primary processor to control the headphone and operate in a low-power state, a cup portion having a microphone to receive an input, a listening sub-system to convert the input into an output signal, and a neural net processor to receive the output signal from the listening sub-system and determine whether to generate a wake signal based on the received output signal.

公开(公告)号：US10581390B2

公开(公告)日：2020-03-03

申请号：US16159281

申请日：2018-10-12

Applicant: Avnera Corporation

Inventor： Ali Hadiashar ,  Wai Laing Lee

IPC: H03G3/20 ,  H03F3/183 ,  H03F1/26 ,  H03F3/187 ,  H03F3/45 ,  H03F3/68

Abstract: A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

公开(公告)号：US10560114B2

公开(公告)日：2020-02-11

申请号：US16174088

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US10516960B2

公开(公告)日：2019-12-24

申请号：US16013073

申请日：2018-06-20

Applicant: Avnera Corporation

Inventor： Colin Doolittle ,  Amit Kumar ,  David Wurtz ,  Michael Wurtz ,  Manpreet Khaira ,  Meenakshi Barjatia

IPC: H04S7/00 ,  H04R1/40 ,  H04R5/02 ,  H04R5/04 ,  H04R3/00 ,  H04S3/00

Abstract: An audio speaker system for a home theater including a number of microphones, a number of speakers, each speaker located at a different location in a room, and a processor electrically connected to the plurality of microphones and wirelessly connected to the plurality of speakers. The processor is configured to generate an audio signal to send to each speaker of the plurality of speakers, output audio from each speaker of the plurality of speakers based on the audio signal, receive the audio at each microphone from each speaker of the plurality of speakers, determine a location of each speaker relative to the plurality of microphones based on the received audio at each microphone, and assign an audio channel to each speaker based on the determined location.

公开(公告)号：US10354639B2

公开(公告)日：2019-07-16

申请号：US15792378

申请日：2017-10-24

Applicant: Avnera Corporation

Inventor： James Scanlan

IPC: G10K11/178 ,  H04R3/00 ,  H04R1/00 ,  H04R1/40 ,  H04R29/00 ,  H04R1/10

Abstract: The disclosure includes a headset comprising one or more earphones including one or more sensing components. The headset also includes one or more voice microphones to record a voice signal for voice transmission. The headset also includes a signal processor coupled to the earphones and the voice microphones. The signal processor is configured to employ the sensing components to determine a wearing position of the headset. The signal processor then selects a signal model for noise cancellation. The signal model is selected from a plurality of signal models based on the determined wearing position. The signal processor also applies the selected signal model to mitigate noise from the voice signal prior to voice transmission.

公开(公告)号：US10200776B2

公开(公告)日：2019-02-05

申请号：US15984068

申请日：2018-05-18

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Shankar Rathoud ,  Mike Wurtz ,  Eric Etheridge ,  Eric Sorensen

IPC: H04R1/10 ,  G10K11/178 ,  H04R3/00 ,  H04R29/00

Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.

公开(公告)号：US10148280B2

公开(公告)日：2018-12-04

申请号：US15853779

申请日：2017-12-23

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/44 ,  H03M1/10 ,  H03M1/18

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

公开(公告)号：US10133293B2

公开(公告)日：2018-11-20

申请号：US15852757

申请日：2017-12-22

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Wai Lee

IPC: G05F3/26 ,  G05F1/10 ,  G05F3/02

Abstract: A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.

公开(公告)号：US09998819B2

公开(公告)日：2018-06-12

申请号：US15662698

申请日：2017-07-28

Applicant: Avnera Corporation

Inventor： Manpreet Singh Khaira ,  Thomas Irrgang

IPC: H04R1/20 ,  H04R1/28 ,  G06F1/16 ,  H04R1/02

CPC classification number: H04R1/20 ,  G06F1/1628 ,  G06F1/1632 ,  G06F2200/1633 ,  G06F2200/1634 ,  H04R1/026 ,  H04R1/28 ,  H04R1/2803 ,  H04R2205/021 ,  H04R2225/33 ,  H04R2400/03 ,  H04R2420/07

Abstract: A case having a recessed holding, an acoustic waveguide, and at least one audio transducer device. The recessed holding well is configured to receive and captively hold a stand-alone keyboard within the recessed holding well. The acoustic waveguide is integrated with a bottom cover of the case and between a bottom surface of the case and the recessed holding well. The at least one audio transducer device is coupled to a signal processing device and the acoustic waveguide. The at least one audio transducer device is configured to generate an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide is configured to receive the audible audio output and generate an enhanced bass audio output.

公开(公告)号：US09832012B2

公开(公告)日：2017-11-28

申请号：US15484408

申请日：2017-04-11

Applicant: AVNERA CORPORATION

Inventor： Samuel J. Peters, II ,  Eric P. Etheridge ,  Victor Lee Hansen ,  Alexander C. Stange

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.