公开(公告)号：US20150372223A1

公开(公告)日：2015-12-24

申请号：US14734960

申请日：2015-06-09

Applicant: Crocus Technology Inc.

Inventor： Bertrand Cambou ,  Ken Mackay ,  Ruby Yehoshua

IPC: H01L43/02 ,  H01L43/08

CPC classification number: G01L1/125 ,  G11C11/161

Abstract: An apparatus includes an elongated strap with a first platform and a second platform linked by a connector that is substantially narrower than the first platform and the second platform, where the first platform and the second platform are each configured to receive a stress sensitive device.

Abstract translation: 一种装置包括具有第一平台的细长带和通过基本上比第一平台和第二平台窄的连接器连接的第二平台，其中第一平台和第二平台各自构造成接收应力敏感装置。

公开(公告)号：US20150357006A1

公开(公告)日：2015-12-10

申请号：US14732561

申请日：2015-06-05

Applicant: Crocus Technology Inc.

Inventor： Thao Tran ,  Douglas Lee ,  Bertrand Cambou

IPC: G11C7/00 ,  G06F3/06

CPC classification number: G11C7/00 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/38

Abstract: An apparatus has magnetic logic units a logic circuit configured to receive a serial input bit stream at an input node. Individual bits of data from the serial input bit stream are serially written into individual magnetic logic units without buffering the serial input bit stream between the input node and the individual magnetic logic units. Individual bits of data from individual magnetic logic units are serially read to produce a serial output bit stream on an output node without buffering the serial output bit stream between the individual magnetic logic units and the output node.

Abstract translation: 一种装置具有磁逻辑单元，逻辑电路被配置为在输入节点处接收串行输入位流。 来自串行输入比特流的单独的数据位被串行地写入单个磁逻辑单元，而不在输入节点和各个逻辑单元之间缓冲串行输入比特流。 串行读取来自各个逻辑单元的单独的数据位以在输出节点上产生串行输出比特流，而不会缓冲各个逻辑单元与输出节点之间的串行输出比特流。

公开(公告)号：US09054029B2

公开(公告)日：2015-06-09

申请号：US14468234

申请日：2014-08-25

Applicant: Crocus Technology Inc.

Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

IPC: H01L27/22 ,  H01L29/82 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

公开(公告)号：US20150077096A1

公开(公告)日：2015-03-19

申请号：US14552338

申请日：2014-11-24

Applicant: Crocus Technology Inc.

Inventor： Bertrand F. Cambou ,  Douglas J. Lee ,  Ken Mackay ,  Barry Hoberman

IPC: G01R33/09 ,  G01D5/16 ,  G01C17/02

CPC classification number: G01D5/12 ,  G01B7/30 ,  G01C17/02 ,  G01D5/16 ,  G01R33/0029 ,  G01R33/096 ,  G01R33/098 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

公开(公告)号：US20140361392A1

公开(公告)日：2014-12-11

申请号：US14468234

申请日：2014-08-25

Applicant: Crocus Technology Inc.

Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

IPC: H01L27/22 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

公开(公告)号：US08652856B2

公开(公告)日：2014-02-18

申请号：US13848641

申请日：2013-03-21

Applicant: Crocus Technology Inc.

Inventor： Jean Pierre Nozieres ,  Jason Reid

IPC: H01L21/00

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L21/00 ,  H01L27/00 ,  H01L43/12

Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.

Abstract translation: 本文公开了通过使用沟槽形成具有薄膜部件的电子器件的方法。 通过在沟槽中沉积薄膜而形成薄膜成分中的一种或多种，​​然后将沉积的薄膜加工成具有所需的厚度。

公开(公告)号：US08611141B2

公开(公告)日：2013-12-17

申请号：US13239168

申请日：2011-09-21

Applicant: Mourad El Baraji ,  Neal Berger

Inventor： Mourad El Baraji ,  Neal Berger

IPC: G11C11/00 ,  G11C11/14

CPC classification number: G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607

Abstract: A memory device includes at least one magnetic random access memory cell, which includes: (1) a magnetic tunnel junction having a first end and a second end; and (2) a strap electrically coupled to the second end of the magnetic tunnel junction. The memory device also includes a bit line electrically coupled to the first end of the magnetic tunnel junction. During a write operation, the bit line is configured to apply a first heating current through the magnetic tunnel junction, and the strap is configured to apply a second heating current through the strap, such that the magnetic tunnel junction is heated to at least a threshold temperature according to the first heating current and the second heating current.

Abstract translation: 存储器件包括至少一个磁性随机存取存储器单元，其包括：（1）具有第一端和第二端的磁性隧道结; 和（2）电耦合到磁性隧道结的第二端的带子。 存储器件还包括电耦合到磁性隧道结的第一端的位线。 在写入操作期间，位线被配置为施加通过磁性隧道结的第一加热电流，并且带被配置为施加第二加热电流通过带，使得磁性隧道结被加热至至少阈值 根据第一加热电流和第二加热电流的温度。

公开(公告)号：US10401442B2

公开(公告)日：2019-09-03

申请号：US14801802

申请日：2015-07-16

Applicant: Crocus Technology Inc.

Inventor： Yaron Oren-Pines ,  Douglas Lee ,  Stuart Rumley

IPC: G01R33/00 ,  G01R33/09 ,  G11C11/16

Abstract: An apparatus includes a circuit including multiple magnetic tunnel junctions, the circuit configured to convert a quadrature modulated magnetic field to a quadrature modulated electrical signal, each magnetic tunnel junction including a storage layer having a storage magnetization and a sense layer having a sense magnetization, each magnetic tunnel junction being configured such that the sense magnetization and impedance of each magnetic tunnel junction vary in response to the quadrature modulated magnetic field. The apparatus further includes a module configured to demodulate the quadrature modulated electrical signal to recover a signal encoded in the quadrature modulated magnetic field.

公开(公告)号：US20180226112A1

公开(公告)日：2018-08-09

申请号：US15891233

申请日：2018-02-07

Applicant: Crocus Technology Inc.

Inventor： Michael GAIDIS ,  Thao TRAN

IPC: G11C11/16 ,  H01L43/08 ,  H01F10/32 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: G11C11/161 ,  G11C11/1673 ,  H01F10/3254 ,  H01F10/3286 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: An apparatus has a reference magnetic tunnel junction with a high aspect ratio including a reference layer with magnetization along a minor axis and a storage layer with magnetization along a major axis. The storage layer magnetization is substantially perpendicular to the magnetization along the minor axis. The magnetization orientation between the minor axis and the major axis is maintained by shape anisotropy caused by the high aspect ratio.

公开(公告)号：US09728233B2

公开(公告)日：2017-08-08

申请号：US14732561

申请日：2015-06-05

Applicant: Crocus Technology Inc.

Inventor： Thao Tran ,  Douglas Lee ,  Bertrand Cambou

IPC: G11C7/10 ,  G11C7/00 ,  G06F3/06 ,  G06F13/38

CPC classification number: G11C7/00 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/38

Abstract: An apparatus has magnetic logic units a logic circuit configured to receive a serial input bit stream at an input node. Individual bits of data from the serial input bit stream are serially written into individual magnetic logic units without buffering the serial input bit stream between the input node and the individual magnetic logic units. Individual bits of data from individual magnetic logic units are serially read to produce a serial output bit stream on an output node without buffering the serial output bit stream between the individual magnetic logic units and the output node.