METAL FOAM PRODUCTION METHOD AND METAL FOAM PRODUCTION APPARATUS

    公开(公告)号:US20210146435A1

    公开(公告)日:2021-05-20

    申请号:US16627906

    申请日:2018-07-02

    Abstract: The present invention provides a metal foam production method that enables a foaming process to be performed at low cost and enables controlling of the shape of metal foam. According to the present invention, a mold that transmits light and a precursor prepared by mixing a metal with a foaming agent are used, and a metal foam is produced by irradiating the precursor with a light transmitted through the mold to thereby heat and foam the precursor so as to obtain a metal foam, while controlling the shape of the metal foam by the mold.

    THERMOELECTRIC CONVERSION ELEMENT
    42.
    发明申请

    公开(公告)号:US20210115076A1

    公开(公告)日:2021-04-22

    申请号:US17050655

    申请日:2019-04-26

    Abstract: Provided is an easy-to-process thermoelectric conversion device whose shape can be freely changed. The device is provided containing electrodes and an ionic solid, wherein the ionic solid has: an anionic heterometal complex aggregated to form a crystal lattice; and a cationic species present in interstices of the crystal lattice, and wherein the anionic heterometal complex includes: a metal M1 selected from the group consisting of the elements of Groups 8, 9 and 10 of the Periodic Table and Cr and Mn; a metal M2 selected from the group consisting of the elements of Groups 11 and 12 of the Periodic Table; and a ligand.

    TUNNELING FIELD EFFECT TRANSISTOR
    46.
    发明申请

    公开(公告)号:US20210005758A1

    公开(公告)日:2021-01-07

    申请号:US16767479

    申请日:2018-11-28

    Abstract: A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer having a first conductive type; a second semiconductor layer having a second conductive type and realizing a heterojunction with respect to the first semiconductor layer in a first region; a gate insulating layer over the second semiconductor layer in the first region; a gate electrode layer over the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer interposed between the first semiconductor layer and the second semiconductor layer in a second region adjacent to the first region toward the second electrode layer.

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