公开(公告)号：US20130078933A1

公开(公告)日：2013-03-28

申请号：US13243986

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H04W88/02 ,  H03B11/00

CPC classification number: H01Q11/12

Abstract: Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

Abstract translation: 超高频电路遭受寄生电阻。 在60GHz，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 此外，使用通孔堆叠的抽头点来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：US20120319673A1

公开(公告)日：2012-12-20

申请号：US13163562

申请日：2011-06-17

Applicant: KhongMeng Tham ,  Zaw Soe

Inventor： KhongMeng Tham ,  Zaw Soe

IPC: G05F3/02

CPC classification number: H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

Abstract translation: 当设计高频（〜60GHz）电路时，本发明消除了对电容器耦合或变压器耦合的需要，以及与这些耦合技术相关联的不期望的寄生电容和电感。 在这个频率下，两个相邻阶段之间的距离需要最小化。 与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。 该谐振电路的引入允许第一级使用金属迹线直接耦合到下一级。 直接耦合技术将高频信号和偏置电压都通过下一级。 与AC耦合或变压器耦合方法相比，直接耦合方法克服了大的管芯面积使用，因为电容器和变压器都不需要在级之间传输高频信号。

公开(公告)号：US20210098892A1

公开(公告)日：2021-04-01

申请号：US17001451

申请日：2020-08-24

Applicant: TENSORCOM, INC.

Inventor： Guang-Fu Cheng

IPC: H01Q21/06 ,  H01Q1/48 ,  H01Q21/00 ,  H01Q1/38

Abstract: An antenna array system and a method for making the antenna system. The system includes at least two antenna elements serving as transmitter elements, and at least two antenna elements serving as receiver elements. Each of the transmitter antenna and receiver antenna elements include a pair of curved arms, wherein a first arm in the pair of curved arms is configured to be connected from a signal trace of the antenna system. The second arm in the pair of curved arms is configured to be connected to a ground plane.

公开(公告)号：US10200024B2

公开(公告)日：2019-02-05

申请号：US15652934

申请日：2017-07-18

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03K5/24 ,  H03H11/48 ,  H03M1/00 ,  H03M1/08 ,  H03M1/18

Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.

公开(公告)号：US10103757B2

公开(公告)日：2018-10-16

申请号：US15505444

申请日：2015-08-25

Applicant: Tensorcom, Inc.

Inventor： KhongMeng Tham ,  Huainan Ma ,  Zaw Soe ,  Ricky Lap Kei Cheung

IPC: H04B1/04 ,  H03D7/12

Abstract: Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

公开(公告)号：US09960948B2

公开(公告)日：2018-05-01

申请号：US15357566

申请日：2016-11-21

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe

IPC: H04B1/10 ,  H04B1/16 ,  H03F3/22 ,  H04L27/38 ,  H03F1/42 ,  H03D7/14 ,  H03D7/16 ,  H03F1/22 ,  H03F3/193 ,  H03F3/45

CPC classification number: H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

Abstract: A receiver comprises a Low Noise Amplifier (LNA) configured to amplify an input signal and a resonant circuit coupled to the LNA. A first switch couples current from the resonant circuit to a first capacitor integrating a first voltage, wherein the first switch is enabled with a clock signal. A second switch couples current from the resonant circuit to a second capacitor integrating a second voltage, wherein the second switch is enabled with an inverse clock signal. A differential amplifier comprises a positive input for receiving the first voltage and a negative input for receiving the second voltage in order to produce a sum and a difference frequency spectrum between a signal spectrum carried within the current and a frequency of the clock signal.

公开(公告)号：US09893692B2

公开(公告)日：2018-02-13

申请号：US15352877

申请日：2016-11-16

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Kevin Jing ,  Steve Gao

IPC: H03G1/00 ,  H03F3/45 ,  H03G5/28

CPC classification number: H03G1/007 ,  H03F3/45197 ,  H03F2200/165 ,  H03F2200/69 ,  H03F2203/45372 ,  H03F2203/45374 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03G5/28 ,  H03H11/1286

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：US20170317668A1

公开(公告)日：2017-11-02

申请号：US15652934

申请日：2017-07-18

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03K5/24 ,  H03H11/48 ,  H03M1/00 ,  H03M1/18 ,  H03M1/08

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier

公开(公告)号：US20170272109A1

公开(公告)日：2017-09-21

申请号：US15505444

申请日：2015-08-25

Applicant: Tensorcom, Inc.

Inventor： KhongMeng Tham ,  Huainan Ma ,  Zaw Soe ,  Ricky Lap Kei Cheung

IPC: H04B1/04 ,  H03D7/12

CPC classification number: H04B1/0475 ,  H03C2200/0058 ,  H03D3/008 ,  H03D3/009 ,  H03D7/125 ,  H03D7/165 ,  H04B1/04 ,  H04B1/0458 ,  H04B2001/0408

Abstract: Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

公开(公告)号：US20170063362A1

公开(公告)日：2017-03-02

申请号：US15340430

申请日：2016-11-01

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03K5/24 ,  H03H11/48

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier

Abstract translation: 电路包括耦合到第一和第二节点的第一放大器; 耦合到第一和第二节点的差分电容性负载，耦合在交叉耦合晶体管电路中的晶体管的漏极之间的差分电容性负载; 耦合到每个晶体管的源极的电流镜; 以及耦合在晶体管的源极之间的电容器。 多个放大器可以耦合到差分电容性负载，其中每个放大器包括比较器的无时钟前置放大器。 放大器可以彼此邻接，使得第一放大器中的第一差分级的有源晶体管在第二放大器中用作相邻差分级的虚拟晶体管