公开(公告)号：US20080038098A1

公开(公告)日：2008-02-14

申请号：US11571428

申请日：2005-07-25

Applicant: Akihiko Ito ,  Kazuyuki Yamashita ,  Yoshihito Kobayashi

Inventor： Akihiko Ito ,  Kazuyuki Yamashita ,  Yoshihito Kobayashi

IPC: H01L21/677

CPC classification number: G01R31/31718 ,  G01R31/2865 ,  G01R31/2868 ,  G01R31/2893 ,  G01R31/31905

Abstract: An apparatus having a plurality of test units (520), a loading transport unit (510) transporting a plurality of electronic devices from a customer tray (4C) to a test tray (4T) before being loaded in a test unit, and a classifying transport unit (530) transporting a plurality of electronic devices from a test tray while classifying them to customer trays in accordance with test results, the loading transport unit being provided at least at a frontmost stage of a plurality of test units, the classifying transport unit being provided at least at a rearmost stage of the plurality of test units, the test tray being successively conveyed from the frontmost stage to the rearmost stage of the plurality of test units in the state carrying electronic devices and returned from the rearmost stage test unit to the frontmost stage test unit.

Abstract translation: 一种具有多个测试单元（520）的装置，在加载到测试单元之前将多个电子设备从客户托盘（4C）传送到测试托盘（4T）的装载传送单元（510），以及 分类运输单元（530），其根据测试结果将多个电子设备从测试盘传送到客户托盘，所述装载运输单元至少设置在多个测试单元的最前面，分类 运送单元至少设置在多个测试单元的最后阶段，测试托盘在携带电子设备的状态下从多个测试单元的最前一阶段到最后阶段连续传送并从最后阶段测试返回 单元到最前台测试单元。

公开(公告)号：US07284213B2

公开(公告)日：2007-10-16

申请号：US11247517

申请日：2005-10-11

Applicant: Jan Fure ,  Richard Schultz ,  Derryl Allman

Inventor： Jan Fure ,  Richard Schultz ,  Derryl Allman

IPC: G06F17/50

CPC classification number: G01R31/31728 ,  G01R31/31718 ,  G01R31/31722 ,  G01R31/318511

Abstract: A system and method for collecting and analyzing optical inspection results obtained during the manufacturing process and comparing those results to actual functional results of a specially designed test vehicle integrated circuit. The test vehicle integrated circuit allows failures to be localized to very small areas, which allows more accurate correlation between inspection faults and functional failures. The correlation of inspection faults to actual functional failures is used to change the sensitivity settings for an optical inspection system to more accurately detect defects that are likely to be functional failures.

Abstract translation: 一种用于收集和分析在制造过程中获得的光学检查结果的系统和方法，并将这些结果与专门设计的测试车辆集成电路的实际功能结果进行比较。 测试车辆集成电路允许将故障定位到非常小的区域，这允许检查故障和功能故障之间的更准确的相关性。 检查故障与实际功能故障的相关性用于改变光学检测系统的灵敏度设置，以更准确地检测可能发生功能故障的缺陷。

公开(公告)号：US20070239308A1

公开(公告)日：2007-10-11

申请号：US11543246

申请日：2006-10-03

Applicant: Raymond Beffa

Inventor： Raymond Beffa

IPC: G06F19/00

CPC classification number: G01R31/2894 ,  G01R31/31718 ,  G01R31/319 ,  G06F11/006 ,  H01L21/67271 ,  H01L22/14 ,  H01L22/20 ,  H01L2223/5444

Abstract: A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.

Abstract translation: 将具有熔丝识别（ID）的类型的集成电路（IC）装置分类到需要增强的可靠性测试的那些装置和需要进行标准测试的装置的方法包括存储制造偏差数据，探针数据和与熔丝ID相关联的测试数据 指示每个设备的每个设备需要增强的可靠性测试或标准测试。 然后在设备的标准测试之前，期间或之后自动读取每个设备的熔丝ID。 然后访问与每个设备的熔丝ID相关联地存储的测试过程要求数据，并且根据所访问的数据将设备分类到需要增强的可靠性测试的设备和需要标准测试的那些设备中。

公开(公告)号：US07254508B2

公开(公告)日：2007-08-07

申请号：US11231722

申请日：2005-09-20

Applicant: Stephen J. Hlotyak

Inventor： Stephen J. Hlotyak

IPC: G06F17/00

CPC classification number: G01R31/31718 ,  G01R31/2834 ,  G01R31/319

Abstract: A method for use with a test system having sites that hold devices under test (DUTs) includes executing a first site loop to iterate through the sites, where the first site loop includes an instruction to program hardware associated with at least one of the sites, and executing a second site loop to process data received from the DUTs, where the second site loop and the first site loop have a same syntax.

Abstract translation: 一种用于具有保存被测设备（DUT）的站点的测试系统的方法包括：执行第一站点循环以遍历站点，其中第一站点循环包括与至少一个站点相关联的程序硬件的指令， 以及执行第二站点循环以处理从DUT接收的数据，其中第二站点循环和第一站点循环具有相同的语法。

公开(公告)号：US07251581B2

公开(公告)日：2007-07-31

申请号：US11460591

申请日：2006-07-27

Applicant: Sani R. Nassif

Inventor： Sani R. Nassif

IPC: G06F7/52

CPC classification number: G01R31/31718 ,  G01R31/318511 ,  G01R31/318533

Abstract: A circuit for computing moment pre-products for statistical analysis reduces data transfer volume for on-chip statistical measurements. The circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the amount of data that must be transferred from a wafer. An integer scaling of the input data is arranged between zero and unity so that the exponentiations all similarly lie between zero and unity. The circuit can use look-up tables and adder/accumulators to accumulate the contributions of each measurement to each exponentiation, or use a multiplier arrangement to determine the contributions. The multipliers can be implemented in the adder/accumulators by clocking the adder/accumulators by corresponding counts determined from the measurement data and lower-order exponentiations. Ranges of the measurement values are determined by capturing maximum and minimum values using comparators as the measurements are input.

Abstract translation: 用于计算用于统计分析的前置产品的电路减少了片上统计测量的数据传输量。 该电路计算一个或多个测量电路的输出的多个指数的和，从而减少必须从晶片传送的数据量。 输入数据的整数缩放被布置在零和单位之间，使得指数都类似地在零和单位之间。 电路可以使用查找表和加法器/累加器来将每个测量的贡献累积到每个乘幂，或者使用乘数布置来确定贡献。 乘法器可以通过对加法器/累加器进行计时，通过从测量数据和低阶指数确定的相应计数来在加法器/累加器中实现。 通过在输入测量值时通过比较器捕获最大值和最小值来确定测量值的范围。

公开(公告)号：US20070159206A1

公开(公告)日：2007-07-12

申请号：US11710466

申请日：2007-02-26

Applicant: Reiner Diewald

Inventor： Reiner Diewald

IPC: G01R31/26

CPC classification number: G01R31/2894 ,  G01R31/2882 ,  G01R31/2893 ,  G01R31/31718

Abstract: A method for testing integrated circuits comprises: generation of a change in an input signal of the integrated circuit, detection of a change in the output signal of the integrated circuit, the change triggered by the change in the input signal when a predetermined condition is satisfied, and a comparison of the detected output signal with at least one predetermined comparison criterion. Whereby, the predetermined condition is derived individually for each integrated circuit from a time response of the output signal.

Abstract translation: 一种用于集成电路测试的方法包括：产生集成电路的输入信号的变化，检测集成电路的输出信号的变化，当满足预定条件时由输入信号的变化触发的变化 以及检测到的输出信号与至少一个预定比较标准的比较。 由此，根据输出信号的时间响应，针对每个集成电路分别导出预定条件。

公开(公告)号：US20070079200A1

公开(公告)日：2007-04-05

申请号：US11499829

申请日：2006-08-04

Applicant: Sassan Tabatabaei ,  Yervant Zorian

Inventor： Sassan Tabatabaei ,  Yervant Zorian

IPC: G01R31/28

CPC classification number: G01R31/31718 ,  G01R31/31715

Abstract: Integrated circuit test circuits may include at least an instruction processor and input-output subsystems. Input-output subsystems are segmented together into input-output subsystem segments. Each input-output subsystem includes an analog wrapper circuit (IW-A) operable to connect an input-output port to analog buses and further operable to isolate the input-output port from the buses, an integrated wrapper for delay test circuit (WI-D) operable to control a delay test sequence, and a soft wrapper circuit operable to control the IW-A and the IW-D, the soft wrapper circuit being directed by the instruction processor.

Abstract translation: 集成电路测试电路可以至少包括指令处理器和输入 - 输出子系统。 输入输出子系统分为输入输出子系统。 每个输入 - 输出子系统包括可操作以将输入 - 输出端口连接到模拟总线的模拟封装电路（IW-A），并进一步可操作以将输入 - 输出端口与总线隔离，用于延迟测试电路（WI- D）可操作以控制延迟测试序列，以及软包装电路，其可操作以控制IW-A和IW-D，软包装电路由指令处理器指导。

公开(公告)号：US07171333B2

公开(公告)日：2007-01-30

申请号：US11109092

申请日：2005-04-19

Applicant: Sani Richard Nassif

Inventor： Sani Richard Nassif

IPC: G06F11/27

CPC classification number: G01R31/31718 ,  G01R31/318511 ,  G01R31/318533

Abstract: An on-wafer method and apparatus for preprocessing measurements of process and environment-dependent circuit performance variables provides new techniques for yield/performance test and analysis. An on-wafer circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the amount of data that must be transferred from the wafer without losing information valuable to the analysis. An integer scaling of the input data is arranged between zero and unity so that the exponentiations all similarly lie between zero and unity. Measurement value ranges are determined by capturing extreme values using comparators as the measurements are input.

Abstract translation: 用于预处理过程和环境相关电路性能变量测量的晶圆方法和装置提供了用于产量/性能测试和分析的新技术。 晶片间电路计算一个或多个测量电路的输出的多个乘积的和，从而减少必须从晶片传送的数据量，而不会丢失对分析有价值的信息。 输入数据的整数缩放被布置在零和单位之间，使得指数都类似地在零和单位之间。 通过在输入测量值时通过比较器捕获极值来确定测量值范围。

公开(公告)号：US07155360B2

公开(公告)日：2006-12-26

申请号：US10995341

申请日：2004-11-24

Applicant: Kensuke Shinohara

Inventor： Kensuke Shinohara

IPC: G06F19/00

CPC classification number: G01R31/31704 ,  G01R31/30 ,  G01R31/31703 ,  G01R31/31718 ,  G01R31/318569 ,  Y10S438/907 ,  Y10S438/98

Abstract: A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a predetermined value, when the pulse signal indicates a specific process variation, by using a transistor of which a channel width and a gate length are set to an unbalanced state, and outputs the predetermined value.

公开(公告)号：US07117063B2

公开(公告)日：2006-10-03

申请号：US11240178

申请日：2005-09-29

Applicant: Raymond J. Beffa

Inventor： Raymond J. Beffa

IPC: G06F19/00

CPC classification number: G01R31/2894 ,  G01R31/31718 ,  G01R31/319 ,  G06F11/006 ,  H01L21/67271 ,  H01L22/14 ,  H01L22/20 ,  H01L2223/5444

Abstract: A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.