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    SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM OTHER ICs ON A SEMICONDUCTOR WAFER
    1.
    发明申请
    SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM OTHER ICs ON A SEMICONDUCTOR WAFER 审中-公开
    用于从半导体波形中的其他IC隔离短路整流电路（IC）的系统

    公开(公告)号：US20090273360A1

    公开(公告)日：2009-11-05

    申请号：US12504001

    申请日：2009-07-16

    申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R31/02 ,  G01R31/26

    CPC分类号： G01R31/025 ,  G01R31/2884

    摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

    摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

    Reduced terminal testing system
    3.
    发明授权
    Reduced terminal testing system 失效
    减少终端测试系统

    公开(公告)号：US06852999B2

    公开(公告)日：2005-02-08

    申请号：US10391067

    申请日：2003-03-17

    申请人： Warren M. Farnworth ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/00 ,  H01L21/8238 ,  H01L23/58 ,  H01L27/10 ,  H01L29/00

    CPC分类号： G01R31/2868 ,  G01R31/2831 ,  G01R31/2841 ,  G01R31/2855 ,  G01R31/2856 ,  G01R31/31701 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.

    摘要翻译： 具有骰子的半导体晶片，其包括当电路接收到具有某些特性的交替信号时被置于模式的电路。 交替信号可以从系统控制器通过晶片上的探针，探针垫和导电路径提供。 在优选实施例中，导电路径同时携带VCC功率信号和交流信号到电路。 然而，交流信号可以在与承载VCC信号的导电路径不同的导电路径上承载。 可以通过交流信号传达大量信息，使其他信号在晶片上的控制，测试，应力和修复骰子方面不必要。 例如，时钟信息可以通过交替信号传送。 可以响应于交变信号的不同特性将电路放置在不同的模式中。 通过每个管芯上的单个接触件接收交流信号和VCC电源信号。 晶片模式控制系统包括系统控制器，用于控制交替信号和其它信号施加到晶片上的骰子。 半导体晶片模式控制系统还可以控制探针定位控制器，该探针定位控制器包括选择性地使探针与探针焊盘接触的探针阵列，由此具有特定特性的交替信号通过探针垫从探针传送到电路 并且导电路径和每个骰子的电路被放置在该模式中。

    Reduced terminal testing system
    7.
    发明授权
    Reduced terminal testing system 有权

    公开(公告)号：US06534785B1

    公开(公告)日：2003-03-18

    申请号：US09638276

    申请日：2000-08-14

    申请人： Warren M. Farnworth ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    发明人： Warren M. Farnworth ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

    IPC分类号： H01L2358

    CPC分类号： G01R31/2868 ,  G01R31/2831 ,  G01R31/2841 ,  G01R31/2855 ,  G01R31/2856 ,  G01R31/31701 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.

    Method of sorting a group of integrated circuit devices for those devices requiring special testing
    8.
    发明授权
    Method of sorting a group of integrated circuit devices for those devices requiring special testing 失效
    对需要特殊测试的那些设备分组一组集成电路设备的方法

    公开(公告)号：US06529793B1

    公开(公告)日：2003-03-04

    申请号：US09607201

    申请日：2000-06-28

    申请人： Raymond J. Beffa

    发明人： Raymond J. Beffa

    IPC分类号： G06F1900

    CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/319 ,  G06F11/006 ,  H01L21/67271 ,  H01L22/14 ,  H01L22/20 ,  H01L2223/5444

    摘要： A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing. The method thus directs those devices needing enhanced reliability testing to such testing without the need for all devices from the same wafer or wafer lot to proceed through special testing.

    摘要翻译： 将具有熔丝识别（ID）的类型的集成电路（IC）装置分类到需要增强的可靠性测试的那些装置和需要进行标准测试的装置的方法包括存储制造偏差数据，探针数据和与熔丝ID相关联的测试数据 指示每个设备的每个设备需要增强的可靠性测试或标准测试。 然后在设备的标准测试之前，期间或之后自动读取每个设备的熔丝ID。 然后访问与每个设备的熔丝ID相关联地存储的测试过程要求数据，并且根据所访问的数据将设备分类到需要增强的可靠性测试的设备和需要标准测试的那些设备中。 因此，该方法将需要增强可靠性测试的那些设备引导到这样的测试，而不需要来自相同晶片或晶片批次的所有器件通过特殊测试进行。

    256 meg dynamic random access memory
    9.
    发明授权
    256 meg dynamic random access memory 有权
    256兆动态随机存取存储器

    公开(公告)号：US06324088B1

    公开(公告)日：2001-11-27

    申请号：US09621012

    申请日：2000-07-20

    申请人： Brent Keeth ,  Layne G. Bunker ,  Raymond J. Beffa ,  Frank F. Ross

    发明人： Brent Keeth ,  Layne G. Bunker ,  Raymond J. Beffa ,  Frank F. Ross

    IPC分类号： G11C502

    CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

    摘要翻译： 一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。 感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。 在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。 提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。 写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。 提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。 多个电压源提供阵列和外围电路中所需的电压。 电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。 提供上电序列电路以控制芯片的上电。 提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。 芯片上还提供电路以支持各种类型的测试模式。

    Method for sorting integrated circuit devices
    10.
    发明授权
    Method for sorting integrated circuit devices 失效
    集成电路器件分类方法

    公开(公告)号：US06307171B1

    公开(公告)日：2001-10-23

    申请号：US09653101

    申请日：2000-08-31

    申请人： Raymond J. Beffa

    发明人： Raymond J. Beffa

    IPC分类号： B07C5344

    CPC分类号： B07C5/344 ,  B07C5/3412 ,  G01R31/01 ,  G01R31/2851 ,  H01L2223/5444 ,  H01L2223/54473

    摘要： An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices. The inventive method is useful for, among other things, culling IC reject bins for shippable IC's, sorting IC's from a wafer lot into those that require enhanced reliability testing and those that do not, and allowing IC's fabricated using both a control fabrication process recipe and a new fabrication process recipe under test to be assembled and tested using the same equipment to reduce unintended test variables introduced when the IC's are assembled and tested separately.

    摘要翻译： 用于分类具有基本上唯一的识别（ID）代码（诸如熔丝ID）的类型的集成电路（IC）装置的创新方法包括：自动读取每个IC器件的ID码，并按照 他们自动读取ID码。 本发明的方法可以与IC制造工艺结合使用，该IC制造工艺包括提供半导体晶片，在每个晶片上制造IC，使IC中的每一个存储其ID代码，将IC中的每一个与其晶片分离以形成IC 骰子，将IC骰子组装到IC器件中，并对IC器件进行测试。 本发明的方法尤其可用于剔除可运输IC的IC拒收箱，将IC从晶片批量分类为需要增强的可靠性测试的IC，并且不允许使用控制制造工艺配方和IC 使用相同的设备组装和测试的新的制造工艺配方，以减少IC独立组装和测试时引入的意外测试变量。