公开(公告)号：US5402428A

公开(公告)日：1995-03-28

申请号：US630210

申请日：1990-12-19

Applicant: Hitoshi Kakuta ,  Yoshihisa Kamo ,  Hajime Aoi

Inventor： Hitoshi Kakuta ,  Yoshihisa Kamo ,  Hajime Aoi

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G06F11/00 ,  G06F1/00 ,  G06F13/00

CPC classification number: G06F11/1076 ,  G06F11/1466 ,  G06F3/0601 ,  G06F2003/0692 ,  G06F2211/109

Abstract: An array disk subsystem including a command selector for separating a signal from a host into a data item and a command, a data dividing unit for subdividing the data item, an ECC generator for producing an ECC for each of the obtained subdata items, a group of data disks for respectively storing thereon the subdata items and the ECCs, a command interpreting unit for interpreting the command, an I/O counter for counting I/O commands in the command, a backup processor for requesting a backup command based on count information of the I/O counter, and a backup unit responsive to the backup command for sequentially reading the subdata items and the ECCs from the data disks to record therein the subdata items and the ECCs.

Abstract translation: 一种阵列磁盘子系统，包括用于将信号从主机分离为数据项和命令的命令选择器，用于细分数据项的数据划分单元，用于为每个所获得的子数据项产生ECC的ECC产生器， 用于分别存储子数据项和ECC的数据磁盘，用于解释命令的命令解释单元，用于对命令中的I / O命令进行计数的I / O计数器，用于根据计数信息请求备份命令的备份处理器 的I / O计数器，以及响应于备份命令的备份单元，用于从数据盘顺序读取子数据项和ECC，以在其中记录子数据项和ECC。

公开(公告)号：US20230336191A1

公开(公告)日：2023-10-19

申请号：US18213766

申请日：2023-06-23

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  G06F11/10 ,  H03M13/11 ,  H03M13/13 ,  G06F12/02 ,  G06F12/06 ,  H03M13/37 ,  H04L1/00 ,  H03M13/00 ,  G11C29/52

CPC classification number: H03M13/154 ,  H03M13/1515 ,  G06F11/1076 ,  H03M13/1191 ,  H03M13/134 ,  G06F12/0238 ,  G06F12/06 ,  G06F11/1096 ,  G06F11/1092 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H04L1/0043 ,  H04L1/0057 ,  H03M13/616 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/6502 ,  G06F2211/1057 ,  G06F2211/109

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

公开(公告)号：US11736125B2

公开(公告)日：2023-08-22

申请号：US17744329

申请日：2022-05-13

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  G11C29/52 ,  G06F11/10 ,  H03M13/11 ,  H03M13/13 ,  G06F12/02 ,  G06F12/06 ,  H03M13/37 ,  H04L1/00 ,  H03M13/00

CPC classification number: H03M13/154 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G11C29/52 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H03M13/6502 ,  H04L1/0043 ,  H04L1/0057 ,  G06F2211/109 ,  G06F2211/1057

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

公开(公告)号：US20190114091A1

公开(公告)日：2019-04-18

申请号：US15782089

申请日：2017-10-12

Applicant: International Business Machines Corporation

Inventor： Susan M. Eickhoff ,  Steven R. Carlough ,  Patrick J. Meaney ,  Stephen J. Powell ,  Jie Zheng ,  Gary A. Van Huben

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1076 ,  G06F11/14 ,  G06F2211/109

Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.

公开(公告)号：US20180314627A1

公开(公告)日：2018-11-01

申请号：US16030232

申请日：2018-07-09

Applicant: Longitude Enterprise Flash S.a.r.l.

Inventor： Evan Orme ,  James G. Peterson ,  Kevin Vigor ,  David Flynn

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/108 ,  G06F12/0246 ,  G06F2003/0694 ,  G06F2211/109 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7208 ,  H04L12/4625 ,  H04L12/6418 ,  H04L12/66 ,  H04L67/1097 ,  H05K7/1444

Abstract: A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit. An index of the data offsets (e.g., second portions of the physical addresses) may be persisted on the storage device. The first portion of the address may be associated with logical addresses of the data in a forward index. The forward index may omit the second portion of the physical addresses, which may reduce the memory overhead of the index and/or allow the forward index to reference larger storage devices. Data of a particular logical address may be accessed using the first portion of the physical address maintained in the forward index, and the second portion of the media address stored on the storage device.

公开(公告)号：US10003358B2

公开(公告)日：2018-06-19

申请号：US15201196

申请日：2016-07-01

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  G06F11/10 ,  H03M13/11 ,  H03M13/13 ,  G06F12/02 ,  G06F12/06 ,  H03M13/37 ,  H03M13/00 ,  H04L1/00 ,  G11C29/52

CPC classification number: H03M13/154 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  G11C29/52 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H03M13/6502 ,  H04L1/0043 ,  H04L1/0057

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

公开(公告)号：US20170017542A1

公开(公告)日：2017-01-19

申请号：US15284019

申请日：2016-10-03

Applicant: LONGITUDE ENTERPRISE FLASH S.A.R.L.

Inventor： David Flynn ,  John Strasser ,  Bill Inskeep

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1092 ,  G06F12/0253 ,  G06F2211/109 ,  G06F2212/2022 ,  H04L12/4625 ,  H04L12/6418 ,  H04L67/1097 ,  H05K7/1444

Abstract: A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising two or more solid-state storage elements. The data segments may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The data arrangement may determine input/output performance characteristics. An optimal adaptive data storage configuration may be based on read and/or write patterns of storage clients, read time, stream time, and so on. Data of failed storage elements may be reconstructed by use of parity data and/or other ECC codewords stored within the array.

Abstract translation: 存储模块被配置为在包括两个或多个固态存储元件的阵列内存储诸如纠错码（ECC）码字的数据段。 数据段可以布置在阵列内的水平布置，垂直布置，混合信道布置和/或垂直条带布置中。 数据排列可以确定输入/输出性能特征。 最佳自适应数据存储配置可以基于存储客户端的读取和/或写入模式，读取时间，流时间等。 可以通过使用存储在该阵列内的奇偶校验数据和/或其他ECC码字来重构失败存储元件的数据。

公开(公告)号：US20160371144A1

公开(公告)日：2016-12-22

申请号：US15253334

申请日：2016-08-31

Applicant: LONGITUDE ENTERPRISE FLASH S.A.R.L.

Inventor： Jeremy Fillingim ,  David Flynn ,  John Strasser ,  Bill Inskeep

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/35 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F9/52 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/0253 ,  G06F2211/109 ,  G06F2212/2022 ,  G11C29/52 ,  H03M13/35 ,  H03M13/353 ,  H04L12/46 ,  H04L12/4625 ,  H04L12/6418 ,  H04L67/1097

Abstract: A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising a plurality of columns. The ECC codewords may comprise ECC codeword symbols. The ECC symbols of a data segment may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The individual ECC symbols may be stored within respective columns of the array (e.g., may not cross column boundaries). Data of an unavailable ECC symbol may be reconstructed by use of other ECC symbols stored on other columns of the array.

公开(公告)号：US09411686B2

公开(公告)日：2016-08-09

申请号：US14331591

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1012 ,  G06F2211/109

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在RAID（独立磁盘冗余阵列）组中的所有消息被编程之后，确定是否已经生成RAID组内的垂直ECC（纠错码）。 处理单元引导DMA（直接存储器访问）控制器从DRAM（动态随机存取存储器）获得垂直ECC，并且当生成RAID组内的垂直ECC时，将垂直ECC存储到缓冲器，从而使垂直 ECC被编程到存储单元。

公开(公告)号：US09292212B2

公开(公告)日：2016-03-22

申请号：US13890438

申请日：2013-05-09

Applicant: CLEVERSAFE, INC.

Inventor： Asimuddin Kazi ,  Jason K. Resch

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G06F11/08 ,  G06F11/00

CPC classification number: G06F11/10 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F11/008 ,  G06F11/08 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1092 ,  G06F2211/109 ,  H03M13/05 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/3761 ,  H03M13/611

Abstract: A method begins by a dispersed storage (DS) processing module detecting, in accordance with a rebuilding process, a storage error of an encoded data slice stored in a storage node of a dispersed storage network (DSN) and identifying the encoded data slice for rebuilding. The method continues with the DS processing module identifying one or more storage traits associated with the encoded data slice and identifying encoded data slices having at least one storage trait in common with the one or more storage traits of the encoded data slice to produce identified encoded data slices. The method continues with the DS processing module prioritizing storage error detection analysis of the identified encoded data slices over other encoded data slices stored in the DSN and when a storage error is detected for one of the identified encoded data slices, identifying the one of the identified encoded data slices for rebuilding.

Abstract translation: 分散存储（DS）处理模块开始的方法是根据重建过程检测存储在分散存储网络（DSN）的存储节点中的编码数据片段的存储错误并识别用于重建的编码数据片段 。 所述方法继续DS处理模块识别与编码数据切片相关联的一个或多个存储特征，并且识别具有与编码数据切片的一个或多个存储特征共同的至少一个存储特征的编码数据切片，以产生识别的编码数据 切片。 该方法继续DS处理模块优先考虑存储在DSN中的其他编码数据片上的所识别的编码数据片的存储错误检测分析，以及当识别出所识别的编码数据片之一时检测到存储错误， 用于重建的编码数据切片。