公开(公告)号：US06408379B1

公开(公告)日：2002-06-18

申请号：US09329718

申请日：1999-06-10

Applicant: Norbert Juffa ,  Stephan Meier ,  Stuart Oberman ,  Scott White

Inventor： Norbert Juffa ,  Stephan Meier ,  Stuart Oberman ,  Scott White

IPC: G06F738

CPC classification number: G06F9/3861 ,  G06F7/483 ,  G06F7/49905 ,  G06F7/4991 ,  G06F9/30014

Abstract: An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.

Abstract translation: 提供了一种用于在微处理器中执行浮点存储指令的装置和方法。 如果浮点存储指令的存储数据对应于微数，并且下溢异常被屏蔽，则可以执行陷阱例程以生成校正的存储数据并完成存储操作。 响应于检测到存储数据对应于微小数字并且下溢异常被屏蔽，可以在启动陷阱例程之前存储存储数据，存储地址信息和操作码信息。 陷阱程序可以配置为访问存储数据，存储地址信息和操作码信息。 陷阱程序可以配置为生成更正的存储数据，并使用存储数据，存储地址信息和操作码信息完成存储操作。

公开(公告)号：US6138135A

公开(公告)日：2000-10-24

申请号：US141246

申请日：1998-08-27

Applicant: Alan H. Karp

Inventor： Alan H. Karp

IPC: G06F7/57 ,  G06F7/38

CPC classification number: G06F7/483 ,  G06F2207/382 ,  G06F7/49905

Abstract: A floating point arithmetic unit provides consistent propagation of NaNs le performing high precision calculations on hardware designed to perform lower precision calculations. In one embodiment, the floating point arithmetic unit is provided with a microcode memory that stores more than one set of NaN propagation rules. In operation, the floating point arithmetic unit accesses one of the sets of NaN propagation rules according to the precision of the calculation being performed. A method of performing calculations in a floating point arithmetic unit includes dynamically determining if a calculation to be performed is to be a quad precision calculation or a double precision calculation. If it is determined that a quad precision calculation is to be performed, quad precision NaN propagation rules are selected and a quad precision calculation is performed using the selected quad precision NaN propagation rules. Likewise, if it is determined that a double precision calculation is to be performed, double precision NaN propagation rules are selected and a double precision calculation is performed using the selected double precision NaN propagation rules. By providing more than one set of NaN propagation rules and selecting one of the sets of NaN propagation rules depending on the precision of the calculation being performed, propagation of NaNs in conformance with IEEE standards can be assured. The method and apparatus are easily extended to higher precision calculations to ensure proper propagation of NaNs regardless of the precision calculation.

Abstract translation: 浮点算术单元提供NaN的一致传播，同时对设计用于执行较低精度计算的硬件执行高精度计算。 在一个实施例中，浮点算术单元设置有存储多于一组NaN传播规则的微代码存储器。 在操作中，浮点算术单元根据正在执行的计算的精度访问NaN传播规则集合中的一个。 在浮点算术单元中执行计算的方法包括动态地确定要执行的计算是四精度计算还是双精度计算。 如果确定要执行四次精度计算，则选择四精度NaN传播规则，并且使用所选择的四次精度NaN传播规则执行四次精度计算。 同样，如果确定要执行双精度计算，则选择双精度NaN传播规则，并且使用所选择的双精度NaN传播规则执行双精度计算。 通过提供多套NaN传播规则，并根据正在执行的计算精度选择一组NaN传播规则，可以确保符合IEEE标准的NaN传播。 该方法和装置易于扩展到更高精度的计算，以确保NaN的适当传播，而不考虑精度计算。

公开(公告)号：US6105047A

公开(公告)日：2000-08-15

申请号：US188868

申请日：1998-11-09

Applicant: Harshvardhan Sharangpani ,  Roger Golliver

Inventor： Harshvardhan Sharangpani ,  Roger Golliver

IPC: G06F7/48 ,  G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F7/38 ,  G06F7/00 ,  G06F15/00

CPC classification number: G06F9/30189 ,  G06F7/48 ,  G06F9/30014 ,  G06F7/49905

Abstract: An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by zero, the selector having a first input and an output, the first input comprising a floating point number, the selector selecting zero to become the output when the floating point number is denormal and the mode bit is set, the selector selecting the floating point number to become the output otherwise.

Abstract translation: 一种用于提高计算机系统中的异常数字处理速度的装置，所述装置包括模式位和选择器，当代数将被零替换时所设置的模式位，所述选择器具有第一输入和输出， 第一输入包括浮点数，当浮点数为非正常且模式位被置位时，选择器选择零成为输出，否则选择器选择浮点数成为输出。

公开(公告)号：US5825678A

公开(公告)日：1998-10-20

申请号：US414858

申请日：1995-03-31

Applicant: Ronald M. Smith

Inventor： Ronald M. Smith

IPC: G06F7/57 ,  G06F9/30 ,  G06F9/308 ,  G06F9/32 ,  G06F7/38 ,  G06F7/00 ,  G06F15/00 ,  H03M7/00

CPC classification number: G06F7/483 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30094 ,  G06F7/49905 ,  G06F7/49942

Abstract: A new Test FP Data Class operation is provided which utilizes a 12-bit mask to determine to which of the 12 possible data classes a floating point number belongs and sets a condition code accordingly. As preferably embodied, a typical IBM System 390 instruction format is adapted to implement a Test FP Data Class operation. The class and sign of the first operand are examined to select one bit from the second-operand address. A condition code of 0 or 1 is set according to whether the selected bit is 0 or 1. The second-operand address is not used to address data; instead, individual bits of the address are used to specify the applicable combinations of operand calls and sign.

Abstract translation: 提供了一种新的测试FP数据类操作，其利用12位掩码来确定浮点数所属的12个可能数据类中的哪一个，并相应地设置条件代码。 如优选实施的，典型的IBM System 390指令格式适于实现测试FP数据类操作。 检查第一个操作数的类和符号以从第二操作数地址中选择一位。 根据所选位是0还是1来设置条件码0或1。第二操作数地址不用于寻址数据; 相反，地址的各个位用于指定操作数调用和符号的适用组合。

公开(公告)号：US5754460A

公开(公告)日：1998-05-19

申请号：US451571

申请日：1995-05-26

Applicant: Hon-Kai John Tam

Inventor： Hon-Kai John Tam

IPC: G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F2207/5353 ,  G06F7/49905 ,  G06F7/49936 ,  G06F7/49994

Abstract: A method for signed integer division. Typically, the two's complement of the dividend is stored as an adjusted dividend. The upper half of the adjusted dividend is shifted left one bit. The LSB of the upper half of the adjusted dividend is set equal to the MSB of the lower half of the adjusted dividend. The lower half of the adjusted dividend is shifted left one bit. The LSB of the lower half of the adjusted dividend is set equal to zero. A temporary register stores the result of subtracting a constant from the adjusted divisor. The temporary register is updated by subtracting it from the adjusted upper dividend, The adjusted divisor is subtracted from the adjusted dividend, then the adjusted dividend is shifted left one bit and stored in the upper half of the adjusted dividend. A temporary remainder is set equal to the upper half of the adjusted dividend. A first temporary quotient is set equal to the lower half of the adjusted dividend. A second temporary quotient is set equal to the first temporary quotient if the sign of the dividend and divisor are equal; if not, the second temporary quotient is set equal to the complement of the first temporary quotient. If the dividend is negative, the remainder is set equal to the temporary remainder; if not, the remainder is set equal to the complement of the temporary remainder. The quotient is then set equal to the second temporary quotient.

Abstract translation: 一种有符号整数除法的方法。 通常情况下，二元红利的补充存储为调整后的股息。 调整后的红利的上半部分向左移一位。 被调整股利上半部分的LSB设定为等于调整后股息下半部分的最高点。 被调整股息的下半部分向左移一位。 调整后的红利的下半部分的LSB设置为零。 临时寄存器存储从调整除数减去常数的结果。 通过从调整后的上分红中减去临时注册表来更新。从被调整股息中减去调整后的除数，然后将调整后的股息左移一位，并存储在被调整股息的上半部分。 临时余款设定为等于调整后股息的上半部分。 第一个临时商定为等于调整后股息的下半部分。 如果股息和除数的符号相等，则第二临时商被设置为等于第一临时商; 如果不是，则将第二临时商设定为等于第一临时商的补数。 如果股利为负数，剩余部分设定为等于临时余额; 如果没有，剩余部分设置为等于临时剩余部分的补码。 然后将商设置为等于第二临时商。

公开(公告)号：US5640578A

公开(公告)日：1997-06-17

申请号：US158742

申请日：1993-11-30

Applicant: Keith Balmer ,  Nicholas Ing-Simmons ,  Karl M. Guttag ,  Robert J. Gove ,  Jeremiah E. Golston ,  Christopher J. Read ,  Sydney W. Poland

Inventor： Keith Balmer ,  Nicholas Ing-Simmons ,  Karl M. Guttag ,  Robert J. Gove ,  Jeremiah E. Golston ,  Christopher J. Read ,  Sydney W. Poland

IPC: G06F3/153 ,  G06F7/575 ,  G06F9/302 ,  G06F9/318 ,  G06F9/32 ,  G06F12/08 ,  G06T1/00 ,  G06T1/20 ,  G06T11/00 ,  G09G5/39 ,  H04N1/387 ,  G06F7/38 ,  G06F7/50

CPC classification number: G06F7/575 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30189 ,  G06F9/30192 ,  G06F2207/382 ,  G06F2207/3828 ,  G06F7/49905

Abstract: An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections. The status detector supplies carry outs from each elementary section (301, 302, 303, 304) not coupled to an adjacent elementary section (301, 302, 303, 304) to the flags register (211). Status signals stored in the flags register (211) influence the combination of inputs formed by the arithmetic logic unit (230) within corresponding sections. An expand circuit (238) expands selected bits of flags register (211) to form a third input to a three input arithmetic logic unit (230).

Abstract translation: 算术逻辑单元（230）可以被划分为多个独立部分（301,302,303,340）。 对应于存储在标志寄存器（211）中的每个部分的进位状态信号的位零，其优选地包括比算术逻辑单元（230）的最大部分数量多的位。 新的状态信号可以覆盖先前的状态信号或旋转存储的比特并存储新的状态信号。 状态寄存器（210）存储确定算术逻辑单元（230）的段数的大小指示符。 状态检测器对于算术逻辑单元（230）的每个基本部分（301,302,303,304）具有零检测器（321,322,323,324）。 当小于最大数量的部分时，这些零信号为“与”（331,332,341）。 多路复用器将基本（311,312,313,314）的进位输出耦合到相邻基本部分（301,302,303,304）的进位，或者不依赖于所选择的部分数量。 状态检测器从没有耦合到相邻基本部分（301,302,303,304）的每个基本部分（301,302,303,304）提供进位到标志寄存器（211）。 存储在标志寄存器（211）中的状态信号影响由相应部分内的算术逻辑单元（230）形成的输入的组合。 扩展电路（238）扩展标志寄存器（211）的所选位以形成三输入算术逻辑单元（230）的第三输入。

公开(公告)号：US5375080A

公开(公告)日：1994-12-20

申请号：US993213

申请日：1992-12-18

Applicant: Daniel Davies

Inventor： Daniel Davies

IPC: G06F7/38 ,  G06F7/02 ,  G06F7/48 ,  G06F7/50 ,  G06F7/505 ,  G06F15/80 ,  G06F7/00

CPC classification number: G06F7/505 ,  G06F7/02 ,  G06F7/026 ,  G06F7/48 ,  G06F9/30021 ,  G06F9/30036 ,  G06F2207/3828 ,  G06F2207/386 ,  G06F7/49905

Abstract: Binary outcome operations are performed on composite operands. A composite operand is an operand that includes plural multi-bit component data items. A binary outcome operation obtains, for each component, a flag bit that depends on the numerical value of the component. A binary outcome operation can be performed by performing an arithmetic operation in parallel on a composite operand in which each component includes more than one bit. The arithmetic operation can add a value, producing a carry signal if a component and the added value together exceed a maximum possible value. Or the arithmetic operation can subtract a value, producing a borrow signal if a component is less than the subtracted value. Also, if the arithmetic operation subtracts a value that is equal to the component, the resulting data item includes only zeros; an operation in parallel can then obtain a single flag bit that is a zero only if the resulting data item includes only zeros. The binary outcome operation can compare each component with a value or can determine whether each component is within a range.

Abstract translation: 在复合操作数上执行二进制结果操作。 复合操作数是包括多个多位组件数据项的操作数。 对于每个组件，二进制结果操作获得取决于组件的数值的标志位。 可以通过在其中每个分量包括多于一个位的合成操作数上并行执行算术运算来执行二进制结果操作。 算术运算可以添加一个值，如果一个分量和一个附加值一起超过一个最大可能的值，产生进位信号。 或者算术运算可以减去一个值，如果一个分量小于减去的值，产生借位信号。 此外，如果算术运算减去与分量相等的值，则生成的数据项仅包括零; 然后，并行的操作可以获得仅当所得数据项仅包括零时为零的单个标志位。 二进制结果操作可以将每个组件与值进行比较，或者可以确定每个组件是否在一个范围内。

公开(公告)号：US4876660A

公开(公告)日：1989-10-24

申请号：US34829

申请日：1987-04-06

Applicant: Robert E. Owen ,  Bruce E. Miller

Inventor： Robert E. Owen ,  Bruce E. Miller

IPC: G06F7/52 ,  G06F7/544

CPC classification number: G06F7/5338 ,  G06F7/544 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30101 ,  G06F2207/3868 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963

Abstract: An integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand and an N-bit wide input register for inputting a Y operand to a multiplier. The multiplier can selectably multiply or concatenate the operands to produce a binary product in the form of a first array of M+N parallel bits. A binary adder adds the binary product to a second array of M+N+P+1 parallel bits and outputs the sum as a Z result in the form of a third array of M+N+P+1 parallel bits. The Z result is stored in a selected one of two accumulators. A feedback path is provided to output selected accumulator contents to the adder as the second binary array of M+N+P+1 bits. Output ports are provided for outputting a selected portion of the accumulator contents. Preferably, the output ports can output the entire M+N+P bits in parallel, as well as any selected portion thereof. Overflow logic can be provided which determines from the (M+ n+P+1)th bit whether an overflow has occurred in the M+N+P bit result. A format adjust circuit is provided between the accumulators and the output ports for shifting the entire output accumulator contents a predetermined number of bits within a range of zero to at least P bits, and preferably P+1 bits, in the direction of the most significant bit.

Abstract translation: 集成电路乘法器 - 累加器架构包括用于输入X操作数的M位宽寄存器和用于将Y操作数输入到乘法器的N位宽输入寄存器。 乘法器可以可选地乘法或级联操作数，以产生M + N并行位的第一阵列形式的二进制乘积。 二进制加法器将二进制乘积加到M + N + P + 1并行比特的第二阵列上，并以M + N + P + 1并行比特的第三阵列的形式输出该和作为Z结果。 Z结果存储在两个累加器中选定的一个中。 提供反馈路径以将选择的累加器内容输出到加法器作为M + N + P + 1位的第二二进制数组。 输出端口用于输出累加器内容的选定部分。 优选地，输出端口可以并行地输出整个M + N + P位以及其任何选定部分。 可以提供从第（M + n + P + 1）位确定M + N + P位结果中是否发生溢出的溢出逻辑。 在累加器和输出端口之间提供格式调整电路，用于将整个输出累加器内容在0到至少P位的范围内移位预定数量的比特，并且最好是P + 1比特 位。

公开(公告)号：US4525780A

公开(公告)日：1985-06-25

申请号：US616773

申请日：1984-05-31

Applicant: Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Craig J. Mundie ,  Stephen I. Schleimer ,  Steven J. Wallach

Inventor： Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Craig J. Mundie ,  Stephen I. Schleimer ,  Steven J. Wallach

IPC: G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/35 ,  G06F9/44 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/08 ,  G06F12/14 ,  G06F9/34 ,  G06F13/00

CPC classification number: G06F9/4428 ,  G01R31/318505 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0875 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/4843 ,  G06F9/54 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

Abstract: A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing a user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object. The system also includes stacks for containing information relating to the current state of execution of the system.

Abstract translation: 数字数据处理系统具有被组织成至少包含操作数和指令的对象的存储器。 每个对象由识别数据处理系统和对象的唯一且永久的标识符代码来标识。 该系统使用保护技术来防止由标识用户的主题号码，用于执行用户过程的系统的处理以及由该用户执行的系统的操作类型由用户标识的用户的未经授权的访问 用户程序。 每个对象的访问控制列表包括具有对对象的访问权限的每个对象的访问控制列表条目，以及用于在允许访问对象之前确认特定活动主体具有对特定对象的访问权限的装置。 系统还包括用于包含与系统的当前执行状态有关的信息的堆栈。

公开(公告)号：US4323981A

公开(公告)日：1982-04-06

申请号：US953743

申请日：1978-10-23

Applicant: Norimitsu Nakamura

Inventor： Norimitsu Nakamura

IPC: G06F7/00 ,  G06F7/76 ,  G06F15/78 ,  G06F7/50

CPC classification number: G06F7/575 ,  G06F15/7896 ,  G06F2207/382 ,  G06F7/49905 ,  G06F7/4991

Abstract: An information processor is provided with a plurality of ALU chips under control of a microprogram and an ALU control circuit for controlling the ALU chips. The ALU control circuit responds to data bus information given thereto to select an ALU chip from which flag data is outputted. The ALU control circuit controls the ALU chip specified by the data bus information to operate it. When a carry is produced in the selected ALU chip, a carry generator is so controlled to produce a given carry signal toward a given ALU chip.

Abstract translation: 信息处理器在微程序控制下设有多个ALU芯片和用于控制ALU芯片的ALU控制电路。 ALU控制电路响应给定的数据总线信息以选择从其输出标志数据的ALU芯片。 ALU控制电路控制由数据总线信息指定的ALU芯片进行操作。 当在选择的ALU芯片中产生进位时，进位发生器被如此控制，以向给定的ALU芯片产生给定的进位信号。