公开(公告)号：US20040124445A1

公开(公告)日：2004-07-01

申请号：US10713054

申请日：2003-11-17

发明人： Masanobu Ogino ,  Yoshikatsu Suto ,  Yoshiro Baba

IPC分类号： H01L021/332 ,  H01L029/80 ,  H01L031/112 ,  C30B001/00

CPC分类号： H01L29/06 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2205 ,  H01L21/2256 ,  H01L29/78

摘要： A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer.

摘要翻译： 公开了一种半导体衬底，其包括含有低浓度杂质的轻掺杂衬底，重掺杂扩散层，形成在轻掺杂衬底的顶部上，杂质浓度高于轻掺杂衬底， 外延层，其形成在重掺杂扩散层的顶部上，并且含有比重掺杂扩散层低的浓度的杂质。

公开(公告)号：US06642121B2

公开(公告)日：2003-11-04

申请号：US10032334

申请日：2001-12-18

申请人： Cateno M. Camalleri ,  Simona Lorenti ,  Denise Cali′ ,  Patrizia Vasquez ,  Giuseppe Ferla

发明人： Cateno M. Camalleri ,  Simona Lorenti ,  Denise Cali′ ,  Patrizia Vasquez ,  Giuseppe Ferla

IPC分类号： H01L218222

CPC分类号： H01L29/66272 ,  H01L21/2256 ,  H01L29/7311

摘要： A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.1 and 120 minutes.

公开(公告)号：US06498079B1

公开(公告)日：2002-12-24

申请号：US09627108

申请日：2000-07-27

申请人： Frank Randolph Bryant ,  Kenneth Wayne Smiley

发明人： Frank Randolph Bryant ,  Kenneth Wayne Smiley

IPC分类号： H01L21225

CPC分类号： H01L21/2256 ,  Y10S438/914 ,  Y10S438/923 ,  Y10S438/924 ,  Y10S438/97 ,  Y10S438/976

摘要： Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

摘要翻译： 可以通过从固体源或掺杂硅玻璃扩散并使用图案化的氮化物层来形成深度轮廓和高掺杂杂质区域。 在图案化区域中留下氧化物蚀刻停止层和多晶硅牺牲层，掺杂剂通过那些层扩散。 多晶硅提供牺牲硅，其用于防止在衬底表面上形成氮化硼，并且还在硅玻璃层的蚀刻期间保护氧化物层。 氧化层然后在去除多晶硅层期间用作蚀刻停止层。 以这种方式，避免了在扩散或随后的蚀刻步骤期间对基板表面的损伤以及昂贵的离子注入机步骤的需要。

公开(公告)号：US06372588B2

公开(公告)日：2002-04-16

申请号：US08837523

申请日：1997-04-21

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L21/2256 ,  H01L21/32155 ,  H01L29/665

摘要： A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.

摘要翻译： 公开了使用固相扩散制造IGFET的方法。 该方法包括在半导体衬底中提供器件区域，在器件区域上形成栅极绝缘体，在栅极绝缘体上形成栅极，在栅极和器件区域上形成绝缘层，在其上形成重掺杂扩散源层 绝缘层，并且通过固相扩散将掺杂剂从扩散源层驱动通过绝缘层进入栅极和器件区域，从而大量掺杂栅极并在器件区域中形成重掺杂的源极和漏极。 优选地，栅极和扩散源层是多晶硅，栅绝缘体和绝缘层是二氧化硅，掺杂剂是硼或硼物质，并且掺杂剂为栅极，源极和漏极提供基本上所有的P型掺杂，从而提供浅 通道结并且减少或消除从孔进入衬底的硼渗透。

公开(公告)号：US20010039094A1

公开(公告)日：2001-11-08

申请号：US08837523

申请日：1997-04-21

发明人： DERICK J. WRISTERS ,  ROBERT DAWSON ,  H. JIM FULFORD, JR. ,  MARK I. GARDNER ,  FREDERICK N. HAUSE ,  MARK W. MICHAEL ,  BRADLEY T. MOORE

IPC分类号： H01L021/336

CPC分类号： H01L29/66575 ,  H01L21/2256 ,  H01L21/32155 ,  H01L29/665

摘要： A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.

摘要翻译： 公开了使用固相扩散制造IGFET的方法。 该方法包括在半导体衬底中提供器件区域，在器件区域上形成栅极绝缘体，在栅极绝缘体上形成栅极，在栅极和器件区域上形成绝缘层，在其上形成重掺杂扩散源层 绝缘层，并且通过固相扩散将掺杂剂从扩散源层驱动通过绝缘层进入栅极和器件区域，从而大量掺杂栅极并在器件区域中形成重掺杂的源极和漏极。 优选地，栅极和扩散源层是多晶硅，栅绝缘体和绝缘层是二氧化硅，掺杂剂是硼或硼物质，并且掺杂剂为栅极，源极和漏极提供基本上所有的P型掺杂，从而提供浅 通道结并且减少或消除从孔进入衬底的硼渗透。

公开(公告)号：US6133126A

公开(公告)日：2000-10-17

申请号：US398688

申请日：1999-09-20

申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC分类号： H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

CPC分类号： H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

摘要： A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

摘要翻译： 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

公开(公告)号：US6008096A

公开(公告)日：1999-12-28

申请号：US790516

申请日：1997-01-29

申请人： Mark I. Gardner ,  Michael Duane ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Michael Duane ,  Daniel Kadosh

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66477 ,  H01L21/2256 ,  H01L21/2652 ,  H01L21/28141 ,  H01L21/823437 ,  H01L29/66545

摘要： A semiconductor process in which the transistor channel is defined by opposing sidewalls of a pair of masking structures formed on an upper surface of a semiconductor substrate. The spacing between the opposed sidewalls is defined by the thickness of the spacer structure formed between the sidewalls. The thickness of the spacer structure is preferably in the range of approximately 0.04 microns. A masking layer is formed on an upper surface of a semiconductor substrate. The masking layer includes first and second masking structures and a channel trench material. Opposing sidewalls of the first and second masking structures are laterally displaced by a channel displacement. The opposing sidewalls together with an upper surface of the semiconductor substrate define a channel trench. The channel trench is displaced above and aligned with a channel region of the semiconductor substrate. The channel trench material fills the channel trench. A mean projected path characteristic of the channel trench material is less than a mean projected path characteristic of the first and second masking structures. A source/drain impurity distribution is implanted into and through the masking layer to selectively introduce a source/drain impurity distribution into a source/drain region of the semiconductor substrate. The source/drain regions of the semiconductor substrate are laterally displaced on either side of the channel region. The channel trench material is then removed and a gate dielectric layer is formed on the floor of the channel trench. Thereafter, the channel trench is filled with a conductive material to form a conductive gate on the gate dielectric.

摘要翻译： 一种半导体工艺，其中晶体管沟道由形成在半导体衬底的上表面上的一对掩模结构的相对侧壁限定。 相对侧壁之间的间隔由形成在侧壁之间的间隔结构的厚度限定。 间隔物结构的厚度优选在约0.04微米的范围内。 掩模层形成在半导体衬底的上表面上。 掩模层包括第一和第二掩模结构和通道沟槽材料。 第一和第二掩蔽结构的相对侧壁被通道位移横向移位。 相对的侧壁与半导体衬底的上表面一起形成通道沟槽。 沟道沟槽位于半导体衬底的沟道区上方并与之对齐。 通道沟槽材料填充沟槽。 通道沟槽材料的平均投影路径特性小于第一和第二掩模结构的平均投影路径特性。 源极/漏极杂质分布被注入并穿过掩模层，以选择性地将源极/漏极杂质分布引入到半导体衬底的源极/漏极区域中。 半导体衬底的源极/漏极区域在沟道区域的任一侧上被横向移位。 然后去除沟道沟槽材料，并且在沟道沟槽的底板上形成栅极电介质层。 此后，沟道沟槽填充有导电材料，以在栅极电介质上形成导电栅极。

公开(公告)号：US5969398A

公开(公告)日：1999-10-19

申请号：US26436

申请日：1998-02-19

申请人： Takashi Murakami

发明人： Takashi Murakami

IPC分类号： H01L29/78 ,  H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/94

CPC分类号： H01L29/66575 ,  H01L21/2236 ,  H01L21/2251 ,  H01L21/2256 ,  H01L21/2257 ,  H01L21/28035 ,  Y10S257/917

摘要： A method for producing a semiconductor device which comprises a step for forming a gate electrode on a main surface of a semiconductor substrate via a gate oxide film, and a step for directing plasma ions with a gas mixture comprising a first gas containing a hydride of an impurity element and a second gas containing a fluoride of the impurity element into a surface of the semiconductor substrate.

摘要翻译： 一种半导体器件的制造方法，包括通过栅氧化膜在半导体衬底的主表面上形成栅电极的步骤，以及用于将气体混合物引导到等离子体离子的步骤，所述气体混合物包含含有氢化物的第一气体 杂质元素和含有杂质元素的氟化物的第二气体进入半导体衬底的表面。

公开(公告)号：US5736446A

公开(公告)日：1998-04-07

申请号：US859753

申请日：1997-05-21

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66492 ,  H01L21/2254 ,  H01L21/2256 ,  H01L21/823468 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/1083 ,  Y10S438/96

摘要： A method of fabricating a MOS device having a gate-side air-gap structure is provided. A nitride spacer for reserving space of the air gap is formed on the substrate adjacent to the gate structure. An amorphous silicon spacer for forming the sidewall spacer and sealing the air gap is formed adjacent to the nitride spacer. The upper portion of the amorphous silicon spacer is heavily doped during the source/drain implantation. After removing the nitride spacer the doped amorphous silicon spacer is oxidized by a wet oxidation process to form a doped oxide spacer. The growing doped oxide spacer will seal the hole for the nitride spacer resulting from the heavily doped upper portion having a higher oxidation rate than that of other portions. Dopants implanted in the amorphous silicon spacer migrate into the substrate and extended ultra-shallow doped regions are formed that reduce the series resistance of the LDD structure.

摘要翻译： 提供一种制造具有栅极侧气隙结构的MOS器件的方法。 在与栅极结构相邻的衬底上形成用于保留空隙的空间的氮化物间隔物。 在氮化物间隔物附近形成用于形成侧壁间隔物并密封气隙的非晶硅间隔物。 在源极/漏极注入期间，非晶硅间隔物的上部被重掺杂。 在去除氮化物间隔物之后，通过湿氧化工艺氧化掺杂的非晶硅间隔物以形成掺杂氧化物间隔物。 生长的掺杂氧化物间隔物将密封由重掺杂的上部产生的氮化物间隔物的孔，其氧化速率高于其它部分的氧化速率。 注入到非晶硅间隔物中的掺杂剂迁移到衬底中，并且形成延伸的超浅掺杂区域，其减小LDD结构的串联电阻。

公开(公告)号：US5407847A

公开(公告)日：1995-04-18

申请号：US124181

申请日：1993-09-20

申请人： James D. Hayden ,  James R. Pfiester ,  David Burnett

发明人： James D. Hayden ,  James R. Pfiester ,  David Burnett

IPC分类号： H01L21/225 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/2256 ,  H01L21/2257 ,  H01L29/66272 ,  H01L29/6656 ,  H01L29/6659 ,  Y10S438/923 ,  Y10S438/965

摘要： A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

摘要翻译： 提供了一种用于在半导体器件中形成超浅硼掺杂区的方法。 在本发明的一个实施例中，提供了一种形成有第一P型区域的N型半导体衬底（15）。 在衬底表面上形成介电层（16），并在介质层（16）上形成掺杂有氟化硼的材料层（17）。 通过从材料层（17）中扩散硼原子，在与第一P型区域相邻的衬底中形成第二P型区域（22），其特征在于衬底表面处的高掺杂剂浓度和均匀的结型材， 通过电介质层（16）并进入衬底（15）。 第二P型区域（22）具有比第一P型区域更靠近衬底表面的非常浅的结深度。