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    Method of forming lightly doped regions in a semiconductor device
    3.
    发明授权
    Method of forming lightly doped regions in a semiconductor device 有权
    在半导体器件中形成轻掺杂区域的方法

    公开(公告)号：US06410410B1

    公开(公告)日：2002-06-25

    申请号：US09852535

    申请日：2001-05-10

    申请人： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek

    发明人： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek

    IPC分类号： H01L21225

    CPC分类号： H01L29/6659 ,  H01L21/2255 ,  H01L29/42368 ,  H01L29/7833

    摘要： A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

    摘要翻译： 公开了一种通过将第一和第二类型的掺杂剂原子扩散到下面的半导体层中而获得半导体层中的轻掺杂区域的方法。 优选地，该方法被应用于在场效应晶体管中形成轻掺杂的源极和漏极区域，以便获得从一般区域到漏极和源极区域所需的逐渐掺杂剂浓度跃迁，以避免热载流子效应。 有利地，掺杂剂原子的扩散在其栅极绝缘层的厚度在其边缘部分增加的氧化步骤期间开始。

    Method and apparatus for self-doping contacts to a semiconductor
    4.
    发明授权
    Method and apparatus for self-doping contacts to a semiconductor 有权
    用于对半导体进行自掺杂接触的方法和装置

    公开(公告)号：US06737340B2

    公开(公告)日：2004-05-18

    申请号：US10176451

    申请日：2002-06-19

    申请人： Daniel L. Meier ,  Hubert P. Davis ,  Ruth A. Garcia ,  Joyce A. Jessup

    发明人： Daniel L. Meier ,  Hubert P. Davis ,  Ruth A. Garcia ,  Joyce A. Jessup

    IPC分类号： H01L21225

    CPC分类号： H01L31/1804 ,  H01L21/228 ,  H01L31/022425 ,  H01L31/0288 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

    摘要： The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature. As the temperature is decreased, the molten silicon reforms through liquid-phase epitaxy and while so doing dopant atoms are incorporated into the re-grown silicon lattice. Once the temperature drops below the silver-silicon eutectic temperature the silicon which has not already been reincorporated into the substrate through epitaxial re-growth forms a solid-phase alloy with the silver. This alloy of silver and silicon is the final contact material, and is composed of eutectic proportions of silicon and silver. Under eutectic proportions there is significantly more silver than silicon in the final contact material, thereby insuring good electrical conductivity of the final contact material.

    摘要翻译： 本发明提供了一种用于产生与硅器件的自掺杂触点的系统和方法，其中接触金属涂覆有掺杂剂层并受到高温，从而使银与硅合金化并同时掺杂硅衬底并形成 低电阻欧姆接触。 自掺杂负极接触可以由非合金的银形成，其可以通过溅射，丝网印刷糊或蒸发施加到硅衬底。 银涂上一层掺杂剂。 一旦施加，银，衬底和掺杂剂被加热到高于Ag-Si共晶温度（但低于硅的熔点）的温度。 银液体比硅底物的共晶比例更高。 然后将温度降低到共晶温度。 随着温度的降低，熔融硅通过液相外延改性，而掺杂剂原子掺入重新生长的硅晶格中。 一旦温度降到银 - 硅共晶温度以下，尚未通过外延再生长再结合到衬底中的硅与银形成固相合金。 这种银和硅的合金是最终的接触材料，由共晶比例的硅和银构成。 在共晶比例下，最终接触材料中的银比硅显着更多，从而确保最终接触材料的良好导电性。

    Solid-source doping for source/drain to eliminate implant damage
    5.
    发明授权
    Solid-source doping for source/drain to eliminate implant damage 有权
    用于源极/漏极的固体源掺杂以消除植入物损伤

    公开(公告)号：US06329273B1

    公开(公告)日：2001-12-11

    申请号：US09430410

    申请日：1999-10-29

    申请人： Timothy Thurgate ,  Carl Robert Huster

    发明人： Timothy Thurgate ,  Carl Robert Huster

    IPC分类号： H01L21225

    CPC分类号： H01L29/66825 ,  H01L21/2257

    摘要： A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped solid source material on portions of the substrate in which source regions are to be formed and diffusing the dopants from the solid source material into the substrate.

    摘要翻译： 一种制造闪速存储器件的方法，其中通过最小化氧化栅极堆叠和衬底的暴露表面来实现最小栅极边缘提升，从衬底各向异性地蚀刻氧化层，在衬底的部分上形成掺杂的固体源材料 其中将形成源区并将掺杂剂从固体源材料扩散到衬底中。

    Method for selective source diffusion
    7.
    发明授权
    Method for selective source diffusion 有权
    选择性源扩散的方法

    公开(公告)号：US06498079B1

    公开(公告)日：2002-12-24

    申请号：US09627108

    申请日：2000-07-27

    申请人： Frank Randolph Bryant ,  Kenneth Wayne Smiley

    发明人： Frank Randolph Bryant ,  Kenneth Wayne Smiley

    IPC分类号： H01L21225

    CPC分类号： H01L21/2256 ,  Y10S438/914 ,  Y10S438/923 ,  Y10S438/924 ,  Y10S438/97 ,  Y10S438/976

    摘要： Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

    摘要翻译： 可以通过从固体源或掺杂硅玻璃扩散并使用图案化的氮化物层来形成深度轮廓和高掺杂杂质区域。 在图案化区域中留下氧化物蚀刻停止层和多晶硅牺牲层，掺杂剂通过那些层扩散。 多晶硅提供牺牲硅，其用于防止在衬底表面上形成氮化硼，并且还在硅玻璃层的蚀刻期间保护氧化物层。 氧化层然后在去除多晶硅层期间用作蚀刻停止层。 以这种方式，避免了在扩散或随后的蚀刻步骤期间对基板表面的损伤以及昂贵的离子注入机步骤的需要。

    Method of forming ONO flash memory devices using rapid thermal oxidation
    8.
    发明授权
    Method of forming ONO flash memory devices using rapid thermal oxidation 有权
    使用快速热氧化形成ONO闪存器件的方法

    公开(公告)号：US06395654B1

    公开(公告)日：2002-05-28

    申请号：US09648077

    申请日：2000-08-25

    申请人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    发明人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    IPC分类号： H01L21225

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

    摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

    摘要翻译： 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 将氮注入到第一层氧化硅中，然后使用快速热工具来加热半导体结构，以退出植入物损伤并将植入的氮扩散到衬底和氧化硅界面，以在该位置形成SiN键 接口。 SiN键是期望的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

    Low cost method of fabricating transient voltage suppressor semiconductor devices or the like
    9.
    发明授权
    Low cost method of fabricating transient voltage suppressor semiconductor devices or the like 失效
    制造瞬态电压抑制半导体器件等的低成本方法

    公开(公告)号：US06248651B1

    公开(公告)日：2001-06-19

    申请号：US09103731

    申请日：1998-06-24

    申请人： Jack Eng ,  Joseph Chan ,  Gregory Zakaluk ,  John Amato ,  Dennis Garbis

    发明人： Jack Eng ,  Joseph Chan ,  Gregory Zakaluk ,  John Amato ,  Dennis Garbis

    IPC分类号： H01L21225

    CPC分类号： H01L21/304 ,  H01L21/2252

    摘要： Transient voltage suppressor semiconductor devices and other semiconductor devices having rigorous requirements for the diffusion and depth of impurities to produce P-N junctions can be fabricated at surprisingly low costs without sacrifice of functional characteristics by subjecting the substrate to a grinding process resulting in a surface short of polishing perfection, thereby to eliminate the time-consuming and hence costly conventional polishing operation, and then diffusing the desired impurity into the substrate from a solid impurity source.

    摘要翻译： 对于产生PN结的杂质的扩散和深度的严格要求的瞬态电压抑制器半导体器件和其他半导体器件可以以惊人的低成本制造，而不牺牲功能特性，通过使衬底经受磨削过程，导致表面缺少抛光 从而消除耗时且因此昂贵的常规抛光操作，然后从固体杂质源将所需的杂质扩散到衬底中。