公开(公告)号：US06642121B2

公开(公告)日：2003-11-04

申请号：US10032334

申请日：2001-12-18

申请人： Cateno M. Camalleri ,  Simona Lorenti ,  Denise Cali′ ,  Patrizia Vasquez ,  Giuseppe Ferla

发明人： Cateno M. Camalleri ,  Simona Lorenti ,  Denise Cali′ ,  Patrizia Vasquez ,  Giuseppe Ferla

IPC分类号： H01L218222

CPC分类号： H01L29/66272 ,  H01L21/2256 ,  H01L29/7311

摘要： A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.1 and 120 minutes.

公开(公告)号：US06806170B2

公开(公告)日：2004-10-19

申请号：US10242293

申请日：2002-09-12

申请人： Peter Ward ,  Simona Lorenti ,  Giuseppe Ferla

发明人： Peter Ward ,  Simona Lorenti ,  Giuseppe Ferla

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022

摘要： A method for forming an interface free layer of silicon on a substrate of monocrystalline silicon is provided. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. A silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700° C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer. Also provided is a method for manufacturing a bipolar transistor.

摘要翻译： 提供了在单晶硅衬底上形成硅界面自由层的方法。 根据该方法，提供具有基本上不含氧化物的表面的单晶硅的衬底。 原位掺杂的硅层在无氧环境和低于700℃的温度下沉积在衬底的表面上，以便产生与衬底相邻的硅层的单晶部分和多晶部分 所述硅层与所述衬底间隔开。 加热硅层，以使硅层的单晶部分通过硅层的多晶部分的一部分生长。 还提供了制造双极晶体管的方法。

公开(公告)号：US07063798B2

公开(公告)日：2006-06-20

申请号：US10726264

申请日：2003-12-02

申请人： Alessio M. D'arrigo Guiseppe ,  Rosario C. Spinella ,  Guiseppe Arena ,  Simona Lorenti

发明人： Alessio M. D'arrigo Guiseppe ,  Rosario C. Spinella ,  Guiseppe Arena ,  Simona Lorenti

IPC分类号： H01L21/00 ,  B44C1/22

CPC分类号： B81C1/00507 ,  G01N27/447 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764

摘要： A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.

摘要翻译： 提出了在包括单晶硅衬底（2）的集成结构（1）中实现埋入微通道（10）的过程。 该工艺在衬底（2）中形成至少一个沟槽（4）。 通过沟槽的各向异性蚀刻从沟槽（4）的小表面端口开始获得微通道（10）。 然后通过生长微晶结构以包围小表面端口将微通道（10）完全掩埋在衬底（2）中。

公开(公告)号：US20120319191A1

公开(公告)日：2012-12-20

申请号：US13597133

申请日：2012-08-28

申请人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

发明人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

摘要： Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

摘要翻译： 一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体中形成沟槽; 沟槽退火成型目的; 并通过外延生长填充半导体材料，以获得具有第二导电类型的第一列。 外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。 含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

公开(公告)号：US07585743B2

公开(公告)日：2009-09-08

申请号：US11724841

申请日：2007-03-16

申请人： Crocifisso Marco Antonio Renna ,  Luigi La Magna ,  Simona Lorenti ,  Salvatore Coffa

发明人： Crocifisso Marco Antonio Renna ,  Luigi La Magna ,  Simona Lorenti ,  Salvatore Coffa

IPC分类号： H01L21/76 ,  H01L21/20 ,  H01L21/36

CPC分类号： B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

摘要： A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.

摘要翻译： 描述了一种用于制造第一浓缩型半导体衬底的方法，至少包括掩埋绝缘腔，包括以下步骤：在半导体衬底上形成多个沟槽，在半导体衬底上形成表面层，以便 在表面上紧密地闭合形成与沟槽的表面 - 远端相对应的至少一个掩埋腔的多个沟槽。

公开(公告)号：US20090159969A1

公开(公告)日：2009-06-25

申请号：US12296921

申请日：2006-04-11

申请人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

发明人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC分类号： H01L27/088 ,  H01L21/20 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

摘要： Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

摘要翻译： 一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体中形成沟槽; 沟槽退火成型目的; 并通过外延生长填充半导体材料，以获得具有第二导电类型的第一列。 外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。 含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

公开(公告)号：US09099322B2

公开(公告)日：2015-08-04

申请号：US13597133

申请日：2012-08-28

申请人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

发明人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/10 ,  H01L29/73 ,  H01L29/739 ,  H01L29/861 ,  H01L29/872

CPC分类号： H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

摘要： Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

摘要翻译： 一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体中形成沟槽; 沟槽退火成型目的; 并通过外延生长填充半导体材料，以获得具有第二导电类型的第一列。 外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。 含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

公开(公告)号：US08304311B2

公开(公告)日：2012-11-06

申请号：US12296921

申请日：2006-04-11

申请人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

发明人： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC分类号： H01L21/336

CPC分类号： H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

摘要： Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

摘要翻译： 一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体中形成沟槽; 沟槽退火成型目的; 并通过外延生长填充半导体材料，以获得具有第二导电类型的第一列。 外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。 含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

公开(公告)号：US20100154876A1

公开(公告)日：2010-06-24

申请号：US12641634

申请日：2009-12-18

申请人： Cateno Marco Camalleri ,  Simona Lorenti ,  Fabrizio Mangano

发明人： Cateno Marco Camalleri ,  Simona Lorenti ,  Fabrizio Mangano

IPC分类号： H01L31/04 ,  H01L31/00 ,  H01L31/18

摘要： A back contact integrated photovoltaic cell includes a substrate having a dielectric surface and a patterned metal layer with parallel spaced alternately positive and negative electrode fingers forming an interdigitated two-terminal structure over the dielectric surface of the substrate. A dielectric filler may be in the interstices of separation between adjacent spaced parts of the patterned metal layer. Parallel spaced strips, alternately of p+ doped polysilicon and of n+ doped polysilicon, may top the positive and negative interdigitated electrode fingers, respectively, and form doped p-type active regions and n-type active regions of the integrated photovoltaic cell, spaced and isolated by a strip of undoped or negligibly doped polysilicon. An n− or p− doped or intrinsic semiconducting layer of at least partly crystallized silicon, forming a semiconductor region of thickness adapted to maximize absorption of photonic energy when illuminated by sunlight, may cover the interdigitated active doped regions.

摘要翻译： 背面接触式集成光伏电池包括具有电介质表面的基板和图案化的金属层，其具有在基板的电介质表面上形成交错的两端结构的交替的正电极指和负电极指。 电介质填料可以在图案化的金属层的相邻间隔部分之间的间隙的间隙中。 平行间隔的条，交替的p +掺杂多晶硅和n +掺杂多晶硅，可以分别在正和负交叉指状电极指的顶部，并形成一体化光伏电池的掺杂p型有源区和n型有源区，隔离和隔离 通过未掺杂或可忽略的掺杂多晶硅的条带。 至少部分结晶的硅的n-或p-掺杂或本征半导体层，形成适于在由太阳光照射时最大化光子能吸收的厚度的半导体区域，可以覆盖交错的有源掺杂区域。

公开(公告)号：US20070181920A1

公开(公告)日：2007-08-09

申请号：US11724841

申请日：2007-03-16

申请人： Crocifisso Renna ,  Luigi La Magna ,  Simona Lorenti ,  Salvatore Coffa

发明人： Crocifisso Renna ,  Luigi La Magna ,  Simona Lorenti ,  Salvatore Coffa

IPC分类号： H01L29/76

CPC分类号： B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

摘要： A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.