公开(公告)号：US5604774A

公开(公告)日：1997-02-18

申请号：US527353

申请日：1995-09-12

Applicant: Yoshinori Rokugo ,  Masaaki Itoh

Inventor： Yoshinori Rokugo ,  Masaaki Itoh

IPC: H03L7/06 ,  H03H17/00 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H04J3/07 ,  H03D3/24

CPC classification number: H03L7/107 ,  H03L7/093 ,  H03L7/0993 ,  H04J3/076

Abstract: Each of primary and secondary random-walk filters has longer and shorter time constants. A multi-valued phase comparator generates a start signal if a phase error generated when an abrupt frequency change occurs exceeds a given value. In response to the start signal, the primary and secondary random-walk filters are set to the shorter time constants. A timer is started by the start signal, and upon elapse of a predetermined period of time, sets the primary and secondary random-walk filters to the longer time constants.

Abstract translation: 每个主要和次要随机游走过滤器具有更长和更短的时间常数。 如果发生突然频率变化时产生的相位误差超过给定值，则多值相位比较器产生起始信号。 响应于起始信号，将主要和次要随机游走滤波器设置为较短的时间常数。 定时器由启动信号启动，经过预定时间后，将主次要随机游走滤波器设定为较长的时间常数。

公开(公告)号：US4845685A

公开(公告)日：1989-07-04

申请号：US74658

申请日：1987-07-17

Applicant: Robert E. Wechsler ,  Joseph A. Horch

Inventor： Robert E. Wechsler ,  Joseph A. Horch

IPC: G01S13/58 ,  G01S15/58 ,  H03L7/099

CPC classification number: G01S15/582 ,  G01S13/586 ,  H03L7/0993

Abstract: A digital phase-locked loop provides substantially real-time measurements of frequency differences between an applied input signal and a reference signal. The system is especially adapted for the measurement of Doppler frequency shift in a Doppler sonar detection system. A two phase clock receives a reference signal and generates complementary clock signals. A phase-frequency detector receives an applied input signal containing a frequency shift and a further reference signal derived and applied in closed loop fashion. Frequency and phase discrepancies between the applied input signal and a second reference signal are gated to a counter to increment the frequency count or blank the frequency count for a predetermined period, thereby to synchronize the second reference signal with the applied input signal in frequency and phase. The frequency difference is detected by counting pulses gated into a divide by N counter thereby to advance or retard the phase of the second reference signal to match the incoming signal under observation. Since no filtering or integration is required, the circuit obtains loop lock within one cycle of the input frequency. An embodiment adapted for pulsed Doppler sonar detection systems employs a secondary counter which is incremented or decremented in accordance with the phase error signal to provide a high resolution low jitter real-time measure of frequency shift.

Abstract translation: 数字锁相环提供了施加的输入信号和参考信号之间的频率差的基本实时测量。 该系统特别适用于多普勒声纳检测系统中的多普勒频移测量。 两相时钟接收参考信号并产生互补时钟信号。 相位频率检测器接收包含频移的施加的输入信号和以闭环方式导出和应用的另外的参考信号。 施加的输入信号和第二参考信号之间的频率和相位偏差被选通到计数器以增加频率计数或将频率计数空白预定的周期，从而使第二参考信号与施加的频率和相位的输入信号同步 。 频率差是通过将门控到N个计数器的脉冲进行计数来检测的，从而推进或延迟第二参考信号的相位以匹配观察到的输入信号。 由于不需要滤波或积分，电路在输入频率的一个周期内获得环路锁定。 适用于脉冲多普勒声纳检测系统的实施例采用根据相位误差信号递增或递减的次计数器，以提供频移的高分辨率低抖动实时测量。

公开(公告)号：US4803680A

公开(公告)日：1989-02-07

申请号：US947240

申请日：1986-12-29

Applicant: Yoshinori Rokugo ,  Botaro Hirosaki

Inventor： Yoshinori Rokugo ,  Botaro Hirosaki

IPC: H03L7/099 ,  H04J3/07

CPC classification number: H04J3/073 ,  H03L7/0993

Abstract: In a destuffing circuit for use in processing an input pulse sequence comprising data pulses, stuffing pulses, and control pulses into an output pulse sequence with reference to a data pulse timing signal, the output pulse sequence is produced with the stuffing and the control pulses removed from the input pulse sequence. A local signal producing arrangement produces a local signal by digital processing a predetermined one of first through M-th timing sequences derived from the data pulse timing signal and a preselected one of first through M-th local sequences derived from the local signal, where M represents a predetermined number. The destuffing circuit further comprises a destuffing arrangment responsive to the input sequence and produces the output pulse sequence by using the data pulse timing signal and the local signal.

Abstract translation: 在用于将包括数据脉冲，填充脉冲和控制脉冲的输入脉冲序列用于参考数据脉冲定时信号处理到输出脉冲序列的去混合电路中，输出脉冲序列产生，填充和控制脉冲被去除 从输入脉冲序列。 本地信号产生装置通过数字处理从数据脉冲定时信号导出的第一至第M定时序列中预定的一个定时序列和从本地信号导出的第一至第M个局部序列中的预选的一个，产生本地信号，其中M 表示预定数量。 去充气电路还包括响应于输入序列的去填充布置，并通过使用数据脉冲定时信号和本地信号产生输出脉冲序列。

公开(公告)号：US4791386A

公开(公告)日：1988-12-13

申请号：US69121

申请日：1987-07-02

Applicant: Nobuo Shiga

Inventor： Nobuo Shiga

IPC: H03L7/06 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107 ,  H03L7/08

CPC classification number: H03L7/089 ,  H03L7/0993 ,  H03L7/107

Abstract: A digital phase-locked loop in which the lead or lag of the phase of the input is compared to the phase of the output of the loop and the occurrences of the advance or retardation are filtered in a random walk filter in order to phase control the output. According to the invention, the time trend of the advance or retardation is determined. If there is a significant run of either advance or retardation, the random walk filter is adjusted so as to more quickly provide correcting output.

Abstract translation: 一个数字锁相环，其中将输入相位的引导或滞后与环路输出的相位进行比较，并且在随机游走滤波器中对先进或延迟的出现进行滤波，以便相位控制 输出。 根据本发明，确定提前或延迟的时间趋势。 如果有一个显着的提前或延迟运行，则调整随机游走滤波器以便更快地提供校正输出。

公开(公告)号：US4573175A

公开(公告)日：1986-02-25

申请号：US531328

申请日：1983-09-12

Applicant: John R. Cressey ,  Stephen A. Miller

Inventor： John R. Cressey ,  Stephen A. Miller

IPC: H03L7/099 ,  H03K3/64

CPC classification number: H03L7/0993

Abstract: Characteristics of a pulse sequence, such as frequency, are controlled in a simple circuit without requirement for specific storage components. The cumulative effect of a sequence of control signals is maintained by providing a phase shift between a pair of waveforms. The phase shift between the waveforms is used to provide a number of control pulses to the circuit for varying the desired characteristic. In a particular embodiment, control signals are externally provided for varying the phase shift between two waveforms. In response to the phase variation, a number of control signals are provided for adding or deleting pulses to a pulse stream. The use of feedback control loops results in repeated addition and/or deletion of pulses to or from the pulse stream, thereby varying the output frequency in accordance with a one time input of the external control signals. In accordance with the principles of the invention, serial or parallel control signals may be provided, and ripple counters (or a combination of ripple and presettable counters) may be used for the frequency control function.

Abstract translation: 诸如频率的脉冲序列的特性在简单的电路中被控制，而不需要特定的存储部件。 通过在一对波形之间提供相移来维持一系列控制信号的累积效应。 波形之间的相移用于向电路提供多个控制脉冲以改变期望的特性。 在特定实施例中，外部提供控制信号以改变两个波形之间的相移。 响应于相位变化，提供多个控制信号用于向脉冲流添加或删除脉冲。 使用反馈控制环路导致与脉冲流的脉冲重复的添加和/或删除，从而根据外部控制信号的一次输入来改变输出频率。 根据本发明的原理，可以提供串行或并行控制信号，并且波纹计数器（或纹波和可预置计数器的组合）可用于频率控制功能。

公开(公告)号：US4191975A

公开(公告)日：1980-03-04

申请号：US935960

申请日：1978-08-23

Applicant: Hugh E. White ,  Robert J. Petri

Inventor： Hugh E. White ,  Robert J. Petri

IPC: H03L7/099 ,  H04L7/033 ,  H04N1/36

CPC classification number: H03L7/0993 ,  H04L7/0332 ,  H04N1/36

Abstract: A digital phase synchronization system in which a received pulse wave is compared in a phase detector with a local pulse wave obtained by frequency dividing the output of a local oscillator. One output of the phase detector is used to control the subtraction or addition of pulses from the local oscillator until phase synchronization is achieved. Another output of the phase detector is used to control the number of pulses which are subtracted or added. The number of pulses subtracted or added is proportional to the phase difference when the phase difference is greater than a predetermined value, and is limited to one or a few pulses when the phase difference is below the predetermined value.

Abstract translation: 一种数字相位同步系统，其中在相位检测器中将接收脉冲波与通过对本地振荡器的输出进行分频而获得的局部脉波进行比较。 相位检测器的一个输出用于控制来自本地振荡器的脉冲的减法或相加，直到实现相位同步。 相位检测器的另一个输出用于控制减去或相加的脉冲数。 当相位差大于预定值时，减去或相加的脉冲数与相位差成比例，当相位差低于预定值时被限制为一个或几个脉冲。

公开(公告)号：US12028082B2

公开(公告)日：2024-07-02

申请号：US17966463

申请日：2022-10-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ja Yol Lee

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/091

CPC classification number: H03L7/0993 ,  H03L7/081 ,  H03L7/091

Abstract: A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.

公开(公告)号：US20130249611A1

公开(公告)日：2013-09-26

申请号：US13991614

申请日：2011-09-28

Applicant: Martin Vandepas

Inventor： Martin Vandepas

IPC: H03L7/099

CPC classification number: H03L7/0993 ,  H03L1/02 ,  H03L1/022 ,  H03L7/0802 ,  H03L2207/50

Abstract: Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL; a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and a voltage adjustment unit to update a power supply level to the DCO based on the compensation signal, wherein the updated power supply level to cause the digital filter to generate the fine code near the middle of an entire range of the fine code across various temperatures, and wherein the digital filter to generate the fine code near the middle of the entire range across power supply drift.

Abstract translation: 这里描述了用于控制数字锁相环（DPLL）中的温度漂移和/或电压漂移的装置，系统和方法。 该装置包括一个包括数字滤波器的DPLL，以产生用于控制DPLL的数字控制振荡器（DCO）的输出信号的频率的精细代码; 逻辑单元，用于监视精细代码并基于精细代码产生补偿信号; 以及电压调整单元，用于基于所述补偿信号来更新对所述DCO的电源电平，其中所述更新的电源电平使得所述数字滤波器在各种温度下的所述精细代码的整个范围的中间附近生成所述精细代码 ，并且其中所述数字滤波器用于在电源漂移之间的整个范围的中间附近产生精细代码。

公开(公告)号：US20080310569A1

公开(公告)日：2008-12-18

申请号：US12155242

申请日：2008-05-30

Applicant: Masahiro Takeuchi

Inventor： Masahiro Takeuchi

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H03L7/0993 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/14

Abstract: Disclosed is a SERDES circuit including a clock and data recovery circuit that allows operational margin in temporal and voltage directions to be measured, using a phase offset signal and a threshold voltage control signal, a pre-emphasis driver circuit and an equalizer circuit in order to reduce ISI on a transmission line, and an optimization control circuit for controlling the overall circuit. The optimization control circuit controls an equalizer control signal that is for adjusting characteristics of the equalizer circuit and a driver control signal that is for adjusting characteristics of the pre-emphasis driver circuit and sets the equalizer control signal and driver control signal so that the operational margin of the clock and data recovery circuit is maximized.

Abstract translation: 公开了一种SERDES电路，其包括使用相位偏移信号和阈值电压控制信号，预加重驱动器电路和均衡器电路来测量在时间和电压方向上的操作余量的时钟和数据恢复电路，以便 减少传输线上的ISI，以及用于控制整个电路的优化控制电路。 优化控制电路控制用于调整均衡器电路的特性的均衡器控制信号和用于调整预加重驱动器电路的特性的驱动器控制信号，并设置均衡器控制信号和驱动器控制信号，使得操作余量 的时钟和数据恢复电路最大化。

公开(公告)号：US20080212574A1

公开(公告)日：2008-09-04

申请号：US11913778

申请日：2005-05-11

Applicant: Tore Andre ,  Anders Lindblad ,  Kenneth Johansson

Inventor： Tore Andre ,  Anders Lindblad ,  Kenneth Johansson

IPC: H04L12/66

CPC classification number: H03L7/091 ,  H03L7/0993 ,  H03L7/181 ,  H04J3/0632 ,  H04J3/0664 ,  H04J3/0697 ,  H04Q2213/13039 ,  H04Q2213/13199 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/13297 ,  H04Q2213/13298 ,  H04Q2213/1336 ,  H04Q2213/13389

Abstract: A forwarding unit such as a DSLAM (8) receives (21) Ethernet packets and forwards information therein on digital subscriber lines (27). For forwarding voice information of received Ethernet packets a reference clock signal is generated by a clock device (28) and provided to modems (23) for the digital subscriber lines. The clock device includes an extraction unit (29) for selecting at least one stream of received Ethernet packets, and a clock signal generating unit, configured as an adaptive clock unit (31), for generating a reference clock signal according to arrival times of packet in selected packet stream or streams. The reference clock signal can be provided to time reference units (25) in the modems. The extraction unit can analyze received Ethernet packets to find streams of packets from one destination to one user, the packets of each of the streams carrying real time information belonging to a real time service and then select one or more streams to be used by the adaptive clock unit.

Abstract translation: 诸如DSLAM（8）的转发单元在数字用户线路（27）上接收（21）以太网分组并转发其中的信息。 为了转发接收到的以太网分组的语音信息，由时钟设备（28）产生参考时钟信号，并提供给用于数字用户线路的调制解调器（23）。 时钟装置包括用于选择接收到的以太网分组的至少一个流的提取单元（29）和配置为自适应时钟单元（31）的时钟信号生成单元，用于根据分组的到达时间生成参考时钟信号 在选定的分组流或流中。 参考时钟信号可以提供给调制解调器中的时间基准单元（25）。 提取单元可以分析接收到的以太网分组，以从一个目的地到一个用户查找分组的流，每个流的分组承载属于实时业务的实时信息，然后选择一个或多个要由自适应 时钟单元