公开(公告)号：US06278395B1

公开(公告)日：2001-08-21

申请号：US09435207

申请日：1999-11-05

Applicant: Masao Ito ,  Takeshi Shigenobu

Inventor： Masao Ito ,  Takeshi Shigenobu

IPC: H03M150

CPC classification number: H03M1/205 ,  H03M1/141

Abstract: An object is to obtain an A/D converter with improved A/D conversion accuracy. The resistor elements (R) and (R) are connected through wiring (L10) (2×L11, L12, 2×L13) mostly with two resistor elements left therebetween. For example, the resistor elements (R1) and (R2) are connected through the partial wiring (L11) and (L13) extended to the left in the diagram, and the resistor elements (R3) and (R4) are connected through the partial wiring (L11) and (L13) extended to the right in the diagram. Thus all of the wiring (L10) connecting electrically adjacent resistor elements (R) and (R) are formed of a combination of partial wiring {2×L11, L12, 2×L13}.

Abstract translation: 目的是获得具有改进的A / D转换精度的A / D转换器。 电阻元件（R）和（R）通过布线（L10）（2xL11，L12,2XL13）连接，其中大部分留有两个电阻元件。 例如，电阻元件（R1）和（R2）通过图中左侧的部分布线（L11）和（L13）连接，电阻元件（R3）和（R4）通过部分 接线图（L11）和（L13）在图中向右延伸。 因此，连接电相邻的电阻元件（R）和（R）的所有布线（L10）由部分布线{2xL11，L12,2×L13}的组合形成。

公开(公告)号：US5633638A

公开(公告)日：1997-05-27

申请号：US498097

申请日：1995-07-05

Applicant: Arnoldus G. W. Venes ,  Bram Nauta

Inventor： Arnoldus G. W. Venes ,  Bram Nauta

IPC: H03M1/12 ,  H03M1/20 ,  H03M1/36 ,  H03M1/38 ,  H03M1/00

CPC classification number: H03M1/205 ,  H03M1/141

Abstract: A folding stage for a folding analog-to-digital converter comprising a plurality of consecutive reference terminals for providing ascending different reference voltages; a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs with each one of the pairs comprising a first transistor having a main current path and a control electrode which is coupled to an input terminal for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node. A dummy structure comprising a first current source, a first dummy transistor having a control electrode coupled to the input terminal, a first main electrode connected to the first current source and a second main electrode coupled to one of the first and second summing nodes, a second current source, and a second dummy transistor having a control electrode coupled to a bias voltage terminal, a first main electrode connected to the second current source and a second main electrode coupled to the other of the first and second summing nodes. The dummy structure reduces capacitive error currents in the differential output current which flows in the summing nodes of the folding stage by providing cancelling currents to the summing nodes.

Abstract translation: 一种用于折叠模数转换器的折叠台，包括用于提供上升不同参考电压的多个连续参考端子; 第一求和节点，第二求和节点和第一输出节点。 多个差分耦合晶体管对，其中每一对包括具有主电流路径的第一晶体管和耦合到输入端子的控制电极，用于接收待折叠的输入电压;以及第二晶体管，具有主电流路径 以及耦合到相应的一个连续参考端子的控制电极。 连续晶体管对的第一晶体管的主电流路径被交替地耦合到第一求和节点和第二求和节点，并且相关联的第二晶体管的主电流路径被交替耦合到第二求和节点和第一求和节点。 一种虚拟结构，包括第一电流源，具有耦合到输入端子的控制电极的第一虚拟晶体管，连接到第一电流源的第一主电极和耦合到第一和第二求和节点之一的第二主电极， 第二电流源和第二虚设晶体管，其具有耦合到偏置电压端子的控制电极，连接到第二电流源的第一主电极和耦合到第一和第二求和节点中的另一个的第二主电极。 虚拟结构通过向求和节点提供消除电流来减少在折叠级的求和节点中流动的差分输出电流中的电容性误差电流。

公开(公告)号：US5012239A

公开(公告)日：1991-04-30

申请号：US396356

申请日：1989-08-21

Applicant: Elmer L. Griebeler

Inventor： Elmer L. Griebeler

IPC: G01D5/244 ,  H03M1/20 ,  H03M1/30

CPC classification number: H03M1/205 ,  F15B15/2846 ,  F15B15/2861 ,  G01D5/24404 ,  H03M1/303

Abstract: A resolution enhancement circuit comprises a voltage divider used to add multiples of two position representing quadrature signals into a plurality of adder output signals having zero crossings during the cycle of the quadrature signals, a digitizer creating a plurality digital signals based on the individual adder output signals and an output logic circuit combining the digital signals into a new pair of digital quadrature signals of increased resolution. The circuit provides information for more precise control of die casting machines and the like.

Abstract translation: 分辨率增强电路包括分压器，用于在正交信号的周期期间将表示正交信号的两个位置的倍数添加到具有过零点的多个加法器输出信号中;数字转换器，基于各个加法器输出信号产生多个数字信号 以及将数字信号组合成具有增加的分辨率的新的一对数字正交信号的输出逻辑电路。 该电路提供了用于更精确地控制压铸机等的信息。

公开(公告)号：US4831379A

公开(公告)日：1989-05-16

申请号：US96793

申请日：1987-09-14

Applicant: Rudy J. van de Plassche

Inventor： Rudy J. van de Plassche

IPC: H03M1/12 ,  G06G7/30 ,  H03M1/14 ,  H03M1/20 ,  H03M1/36

CPC classification number: H03M1/205 ,  G06G7/30 ,  H03M1/141

Abstract: The invention centers around a system for interpolating between multiple pairs of main complementary signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is done with two strings (12) of a selected number of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.NO -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. The interpolated signals are taken from other pairs of corresponding nodes along the strings. The interpolation system is particularly suitable for use in an analog-to-digital converter of the folding type.

Abstract translation: 本发明围绕用于在多对主互补信号之间进行内插以产生另外的互补信号对的系统。 输入电路（10）提供主信号。 内插使用选定数量的阻抗元件（R0-RN-1和RNO-RNN-1）的两个串（12）完成。 每对主信号被提供给沿着串的一对相应的节点。 内插信号是沿着串的其他对相应节点取的。 插值系统特别适用于折叠型的模数转换器。

公开(公告)号：US09389635B2

公开(公告)日：2016-07-12

申请号：US14935679

申请日：2015-11-09

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  James E. Burnette, II

IPC: G01R31/28 ,  G06F1/04 ,  G01R31/3185 ,  G01R31/317 ,  H03M1/08 ,  H03M1/20 ,  H04L1/20 ,  G11B20/10

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

公开(公告)号：US20160134298A1

公开(公告)日：2016-05-12

申请号：US14538013

申请日：2014-11-11

Applicant: MediaTek Inc.

Inventor： Wen-Hua CHANG

IPC: H03M1/20 ,  H03M1/36

CPC classification number: H03M1/205 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An ADC is provided. The ADC includes a plurality of pre-amplifiers, dynamic comparators coupled to the pre-amplifiers, interpolators and an encoder. Each pre-amplifier provides a pair of differential outputs according to a pair of differential analog signals and a first reference voltage and a second reference voltage different from the first reference voltage. Each dynamic comparator provides a first comparing signal and a second comparing signal according to the pair of differential outputs of the corresponding pre-amplifier. Each interpolator provides an interpolating signal according to the first and second comparing signals of two of the dynamic comparators. The encoder provides a digital output according to the interpolating signals. The first and second comparing signals are the same in a reset phase, and the first and second comparing signals are complementary according to the pair of differential outputs of the corresponding pre-amplifier in an evaluation phase.

Abstract translation: 提供了一个ADC。 ADC包括多个预放大器，耦合到前置放大器，内插器和编码器的动态比较器。 每个前置放大器根据一对差分模拟信号和不同于第一参考电压的第一参考电压和第二参考电压提供一对差分输出。 每个动态比较器根据相应的前置放大器的差分输出对提供第一比较信号和第二比较信号。 每个内插器根据两个动态比较器的第一和第二比较信号提供内插信号。 编码器根据内插信号提供数字输出。 第一和第二比较信号在复位阶段相同，并且第一和第二比较信号根据评估阶段中对应的前置放大器的差分输出的对而互补。

公开(公告)号：US08362937B2

公开(公告)日：2013-01-29

申请号：US12791963

申请日：2010-06-02

Applicant: Shine Chung

Inventor： Shine Chung

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/1038 ,  H03M1/205

Abstract: An integrated circuit that is capable of converting an analog signal to at least one digital signal is provided. The integrated circuit includes a first input end capable of receiving a first analog signal. A first set of 2n-1 inverters are capable of quantizing the first analog signal and outputting a first set of 2n-1 digital values. Each of the first set of 2n-1 digital values is either 0 or 1. A first adder is coupled with the first set of 2n-1 inverters. The first adder is capable of summing the first set of 2n-1 digital values, outputting a first integer value that is capable of corresponding to at least one digital signal.

Abstract translation: 提供了能够将模拟信号转换为至少一个数字信号的集成电路。 集成电路包括能够接收第一模拟信号的第一输入端。 第一组2n-1个反相器能够量化第一模拟信号并输出​​第一组2n-1个数字值。 第一组2n-1数字值中的每一个都是0或1.第一加法器与第一组2n-1个反相器耦合。 第一加法器能够对第一组2n-1数字值求和，输出能够对应于至少一个数字信号的第一整数值。

公开(公告)号：US08130131B2

公开(公告)日：2012-03-06

申请号：US12763439

申请日：2010-04-20

Applicant: Yuji Nakajima

Inventor： Yuji Nakajima

IPC: H03M1/34

CPC classification number: H03M1/002 ,  H03M1/205 ,  H03M1/365

Abstract: Provided is an interpolating A/D converter including a reference voltage generation circuit, an analog signal input circuit, a preamplifier group including a plurality of preamplifiers, and an interpolation circuit including a plurality of resistors. Reference voltages from the reference voltage generation circuit and an analog signal from the analog signal input circuit are input to the preamplifier group. The interpolation circuit outputs an interpolation signal by interpolating output signals of the preamplifier group. The preamplifiers amplify a differential voltage when a differential voltage between the analog signal and the reference voltages is smaller than a specified value, and the current flow of which is stopped when it is larger than the specified value. The plurality of resistors are connected in series between the adjacent amplifiers.

Abstract translation: 提供了一种包括参考电压产生电路，模拟信号输入电路，包括多个前置放大器的前置放大器组以及包括多个电阻器的内插电路的内插A / D转换器。 来自参考电压产生电路的参考电压和来自模拟信号输入电路的模拟信号被输入到前置放大器组。 内插电路通过内插前置放大器组的输出信号来输出插值信号。 当模拟信号和参考电压之间的差分电压小于指定值时，前置放大器放大差分电压，当电流大于指定值时，其电流将停止。 多个电阻串联连接在相邻的放大器之间。

公开(公告)号：US08106806B2

公开(公告)日：2012-01-31

申请号：US12662350

申请日：2010-04-13

Applicant: Junji Toyomura ,  Miho Inoue

Inventor： Junji Toyomura ,  Miho Inoue

IPC: H03M1/36

CPC classification number: H03M1/205 ,  H03M1/365

Abstract: Disclosed herein is an AD converter, including, a reference voltage generator, a plurality of amplifiers, a plurality of averaging resistance elements, and a plurality of first averaging auxiliary circuits each including a first amplifier and a first resistance element.

Abstract translation: 本文公开了一种AD转换器，包括参考电压发生器，多个放大器，多个平均电阻元件以及多个第一平均辅助电路，每个包括第一放大器和第一电阻元件。

公开(公告)号：US20100149009A1

公开(公告)日：2010-06-17

申请号：US12637211

申请日：2009-12-14

Applicant: Tomohiko ITO ,  Tetsuro Itakura

Inventor： Tomohiko ITO ,  Tetsuro Itakura

IPC: H03M1/10

CPC classification number: H03M1/1023 ,  H03M1/0682 ,  H03M1/205 ,  H03M1/365 ,  H03M1/745

Abstract: There is disclosed a calibration method for an A/D converter. The A/D converter includes a first amplifier to amplify first and second voltage signals, a second amplifier to amplify the first and second voltage signals amplified by the first amplifier, and a comparator to compare the first and second voltage signals amplified by the second amplifier. The calibration method performs short-circuiting input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a first result, calibrating output voltage of the second amplifier according to the first result, short-circuiting input ports of the first amplifier, opening the short-circuited input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a second result, and calibrating output voltage of the first amplifier according to the second result.

Abstract translation: 公开了一种用于A / D转换器的校准方法。 A / D转换器包括：放大第一和第二电压信号的第一放大器;放大由第一放大器放大的第一和第二电压信号的第二放大器;以及比较器，用于比较由第二放大器放大的第一和第二电压信号; 。 校准方法执行第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第一结果，根据第一结果校准第二放大器的输出电压，短路输入端口 第一放大器，打开第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第二结果，并根据第二结果校准第一放大器的输出电压。