公开(公告)号：US20230418985A1

公开(公告)日：2023-12-28

申请号：US17852083

申请日：2022-06-28

Applicant: Amazon Technologies, Inc.

Inventor： Ali Rahbar ,  Nhon Toai Quach ,  Samatha Gummalla ,  Diana Chang ,  Donghyun Choi ,  Utpal Vijaysinh Solanki ,  Gururaj Ananthateerta

IPC: G06F21/72 ,  G06F21/79 ,  G06F21/60 ,  G06F21/55

CPC classification number: G06F21/72 ,  G06F21/79 ,  G06F21/602 ,  G06F21/554

Abstract: Techniques for providing remote attestation at an integrated circuit device are described. The integrated circuit device may include a memory. The integrated circuit device may also include a write bitmap comprising a bitmap that tracks the write addresses of detected memory write operations to the memory. The integrated circuit device may further include a security subsystem configured to send one or more address ranges of interest to the write bitmap and obtain a bitmap status from the write bitmap indicating that a write address within the one or more address ranges of interest was detected.

公开(公告)号：US11842781B2

公开(公告)日：2023-12-12

申请号：US17567705

申请日：2022-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Shao-Yu Chou ,  Yih Wang

IPC: G11C17/16 ,  G11C7/24 ,  G11C8/14 ,  G11C17/18 ,  G06F21/79 ,  G06F12/14

CPC classification number: G11C17/16 ,  G06F12/14 ,  G06F21/79 ,  G11C7/24 ,  G11C8/14 ,  G11C17/18

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

公开(公告)号：US11841951B2

公开(公告)日：2023-12-12

申请号：US17231216

申请日：2021-04-15

Applicant: Dell Products, L.P.

Inventor： Sumanth Vidyadhara ,  Vivek Viswanathan Iyer

IPC: G06F21/57 ,  G06F21/79 ,  H04L67/51 ,  H04L41/34

CPC classification number: G06F21/575 ,  G06F21/572 ,  G06F21/79 ,  H04L41/34 ,  H04L67/51

Abstract: Systems and methods are provided for remotely supporting managed hardware components of an IHS (Information Handling System). Prior to booting an operating system of the IHS, the managed hardware components are enumerated as supporting remote management and a network stack is created in a secured IHS memory, where the network stack is for transfer of remote device management communications directed at the managed hardware components. Still prior to booting the operating system, the IHS chipset is configured to route device management messages received from remote management tools to the network stack. After booting the operating system, a secure remote management session is established between a remote management tool and an IHS device management agent. During operation of the device management agent in the booted operating system, device management messages are retrieved from the network stack and decoded device management messages are delivered to a managed hardware component.

公开(公告)号：US20230394143A1

公开(公告)日：2023-12-07

申请号：US18104079

申请日：2023-01-31

Applicant: Micron Technology, Inc

Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

IPC: G06F21/55 ,  G06F21/57 ,  G06F21/79

CPC classification number: G06F21/556 ,  G06F21/575 ,  G06F21/79

Abstract: Methods, systems, and devices for protective actions for a memory device based on detecting an attack are described. In some systems, a memory device may detect whether a fault is injected into the memory device. The memory device may apply a delay during boot up if a fault is detected. To ensure the delay is applied, the memory device may default to applying the delay and may remove an indication to apply the delay if a fault is not detected. Additionally or alternatively, the memory device may erase information from non-volatile memory during boot up, for example, if a fault is detected. The memory device may be configured to ensure at least a specific portion of memory resources (e.g., resources configured to store sensitive information) is erased during boot up. In some examples, the memory device may store data using a stream cipher to improve security of the data.

公开(公告)号：US20230385461A1

公开(公告)日：2023-11-30

申请号：US18446132

申请日：2023-08-08

Applicant: PROTON WORLD INTERNATIONAL N.V.

Inventor： Olivier VAN NIEUWENHUYZE

IPC: G06F21/79 ,  G06F21/57 ,  G06F21/64 ,  G06F21/72

CPC classification number: G06F21/79 ,  G06F21/575 ,  G06F21/107 ,  G06F21/72 ,  G06F21/64

Abstract: A method of checking the authenticity of at least a first portion of the content of a non-volatile memory of an electronic device including a microcontroller and an embedded secure element is disclosed. The method includes starting the microcontroller with instructions stored in a first secure memory area associated with the microcontroller and starting the secure element. The secure element has a plurality of decipher keys, each associated with a portion of the content of a second reprogrammable non-volatile memory area associated with the microcontroller. The secure element performs a signature check on a first portion of the content of the second area. If the signature is verified, the secure element sends the decipher key associated with the first portion to the microcontroller. If the signature is not verified, the secure element executes a signature check on another portion of the content of the second memory area.

公开(公告)号：US20230367912A1

公开(公告)日：2023-11-16

申请号：US18311981

申请日：2023-05-04

Applicant: Infineon Technologies AG

Inventor： Marcus Janke ,  Steffen Sonnekalb

IPC: G06F21/64 ,  G06F21/79

CPC classification number: G06F21/64 ,  G06F21/79

Abstract: A semiconductor chip apparatus including a memory having a plurality of memory locations, a memory access element, and an integrity check device configured to store a reference value for a check function over values stored in the memory locations and, in a case of write access to a memory location, configured to update a check value with the value to be written by the write access if the check value represents the value stored in the memory location prior to the write access, and configured to compare the reference value with the check value after the check value has been generated and output a signal depending on a result of the comparison.

公开(公告)号：US11797717B2

公开(公告)日：2023-10-24

申请号：US16765224

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolo Izzo

IPC: G06F21/85 ,  G06F12/02 ,  G06F21/60 ,  G06F21/79 ,  G06F12/14

CPC classification number: G06F21/85 ,  G06F12/0246 ,  G06F12/1408 ,  G06F21/602 ,  G06F21/79

Abstract: The present disclosure relates to apparatuses and methods for memory management. The disclosure further relates to an interface protocol for flash memory devices including at least a memory array and a memory controller coupled to the memory array.
A host device is coupled to the memory device through a communication channel and a hardware and/or software full encryption-decryption scheme is adopted in the communication channel for data, addresses and commands exchanged between the host device and the memory array.

公开(公告)号：US20230325541A1

公开(公告)日：2023-10-12

申请号：US18208585

申请日：2023-06-12

Applicant: Micron Technology, Inc.

Inventor： Walter Andrew Hubis

IPC: G06F21/79 ,  G11C16/34 ,  G06F21/60 ,  G06F21/57

CPC classification number: G06F21/79 ,  G06F21/572 ,  G06F21/602 ,  G11C16/3472

Abstract: A processing device sets a first flag that indicates whether a first critical security parameter (CSP) file exists. The first CSP file includes a first set of CSPs for a memory device. The processing device sets a second flag that indicates whether the first CSP file is valid. The processing device sets a third flag that indicates whether a second CSP file exists. The second CSP file includes a second set of CSPs for the memory device. The processing device sets a fourth flag that indicates whether the second critical security parameter file is valid. The processing device selects one of the first or second CSP file as an active CSP file based on an evaluation of the first, second, third, and fourth flags.

公开(公告)号：US20230325540A1

公开(公告)日：2023-10-12

申请号：US18130362

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  John Eric Linstadt

IPC: G06F21/79 ,  G06F21/85 ,  G06F21/60

CPC classification number: G06F21/79 ,  G06F21/85 ,  G06F21/602

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to access a memory. Memory interface circuitry couples to the memory. Message authentication circuitry performs a verification operation on the received request. Selective containment circuitry, during a containment mode of operation, (1) inhibits changes to the memory in response to the at least one command until completion of the verification operation, and (2) during performance of the verification operation, carries out at least one non-memory modifying sub-operation associated with the at least one command.

公开(公告)号：US11782716B2

公开(公告)日：2023-10-10

申请号：US17517580

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Michael LeMay ,  Vedvyas Shanbhogue ,  Deepak Gupta ,  Ravi Sahita ,  David M. Durham ,  Willem Pinckaers ,  Enrico Perla

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/46 ,  G06F16/901 ,  G06F9/455 ,  G06F12/14 ,  G06F21/52 ,  G06F21/79 ,  G06F9/35

CPC classification number: G06F9/30145 ,  G06F9/3836 ,  G06F9/449 ,  G06F9/468 ,  G06F16/9017

Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.