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公开(公告)号：US12073169B2
公开(公告)日：2024-08-27
申请号：US18446684
申请日：2023-08-09
发明人： Meng-Sheng Chang , Shao-Yu Chou , Yao-Jen Yang , Chen-Ming Hung
IPC分类号： G06F7/50 , G06F30/392 , G11C17/16 , G11C17/18 , H01L23/528 , H10B20/20 , H01L23/525
CPC分类号： G06F30/392 , G11C17/16 , G11C17/18 , H01L23/528 , H10B20/20 , H01L23/5252
摘要： An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.
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公开(公告)号：US11942168B2
公开(公告)日：2024-03-26
申请号：US18295148
申请日：2023-04-03
发明人： Meng-Sheng Chang , Yao-Jen Yang
IPC分类号： G11C17/16 , G06F30/392 , G11C17/18 , H01L23/525 , H01L27/02 , H10B20/20 , G06F119/18
CPC分类号： G11C17/16 , G06F30/392 , G11C17/18 , H01L23/5256 , H01L27/0207 , H10B20/20 , G06F2119/18
摘要： An IC structure includes a first active area including a first plurality of fin structures extending in a first direction, a second active area including a second plurality of fin structures extending in the first direction, an electrical fuse (eFuse) extending in the first direction between the first and second active areas and electrically connected to each of the first and second pluralities of fin structures, a first plurality of gate structures extending over the first active area perpendicular to the first direction, a second plurality of gate structures extending over the second active area in the second direction, a first signal line extending in the first direction adjacent to the first active area and electrically connected to the first plurality of gate structures, and a second signal line extending in the first direction adjacent to the second active area and electrically connected to the second plurality of gate structures.
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公开(公告)号：US11842781B2
公开(公告)日：2023-12-12
申请号：US17567705
申请日：2022-01-03
发明人： Meng-Sheng Chang , Yao-Jen Yang , Shao-Yu Chou , Yih Wang
摘要： A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.
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公开(公告)号：US11621046B2
公开(公告)日：2023-04-04
申请号：US17541245
申请日：2021-12-02
发明人： Meng-Sheng Chang , Yao-Jen Yang
IPC分类号： G11C17/16 , G06F30/392 , G11C17/18 , H01L23/525 , H01L27/02 , H01L27/112 , G06F119/18
摘要： An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.
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公开(公告)号：US11176969B2
公开(公告)日：2021-11-16
申请号：US16523953
申请日：2019-07-26
发明人： Meng-Sheng Chang , Min-Shin Wu , Yao-Jen Yang
摘要： A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line.
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公开(公告)号：US20200058361A1
公开(公告)日：2020-02-20
申请号：US16419648
申请日：2019-05-22
发明人： Meng-Sheng Chang , Yao-Jen Yang
IPC分类号： G11C17/16 , G11C17/18 , H01L23/525 , H01L27/112 , H01L27/02 , G06F17/50
摘要： A circuit includes an eFuse and a first program device coupled in series between a bit line and a program node, and a second program device configured in parallel with the first program device. The first program device and the second program device are separately controllable.
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公开(公告)号：US20240071536A1
公开(公告)日：2024-02-29
申请号：US18447826
申请日：2023-08-10
发明人： Meng-Sheng Chang , Yao-Jen Yang , Min-Shin Wu
IPC分类号： G11C17/16 , G11C11/4074 , G11C11/408 , G11C11/4094 , G11C11/56
CPC分类号： G11C17/16 , G11C11/4074 , G11C11/4085 , G11C11/4094 , G11C11/5642
摘要： A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.
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公开(公告)号：US11856760B2
公开(公告)日：2023-12-26
申请号：US17463172
申请日：2021-08-31
发明人： Chien-Ying Chen , Yao-Jen Yang
IPC分类号： H10B20/20 , G06F30/392
CPC分类号： H10B20/20 , G06F30/392
摘要： A one-time programmable (OTP) bit cell includes a substrate including a front side and a back side, an active area on the front side, a first read transistor including a first gate and a first portion of the active area intersected by the first gate, a program transistor including a second gate and a second portion of the active area intersected by the second gate, a first electrical connection to the first gate, a second electrical connection to the second gate, and a third electrical connection to the active area. At least one of the first, second, or third electrical connections includes a metal line positioned on the back side.
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公开(公告)号：US11803683B2
公开(公告)日：2023-10-31
申请号：US17342295
申请日：2021-06-08
发明人： Yao-Jen Yang , Meng-Sheng Chang
IPC分类号： G06F30/00 , G06F30/392 , H01L27/02 , H01L27/12 , H01L27/118 , G06F30/398 , G03F1/20
CPC分类号： G06F30/392 , G06F30/398 , H01L27/0207 , H01L27/11807 , H01L27/1222 , G03F1/20 , H01L2027/11874
摘要： A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.
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公开(公告)号：US20220246225A1
公开(公告)日：2022-08-04
申请号：US17726152
申请日：2022-04-21
发明人： Meng-Sheng Chang , Yao-Jen Yang , Min-Shin Wu
IPC分类号： G11C17/16 , G11C11/408 , G11C11/56 , G11C11/4074 , G11C11/4094
摘要： A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.
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