公开(公告)号：US20230196086A1

公开(公告)日：2023-06-22

申请号：US18174021

申请日：2023-02-24

申请人： MICROSOFT TECHNOLOGY LICENSING, LLC

发明人： Amol A AMBARDEKAR ,  Boris BOBROV ,  Kent D. CEDOLA ,  Chad Balling MCBRIDE ,  George PETRE ,  Larry Marvin WALL

IPC分类号： G06N3/063 ,  G06F7/499 ,  G06F7/523 ,  G06F7/57 ,  G06F9/30

CPC分类号： G06N3/063 ,  G06F7/57 ,  G06F7/523 ,  G06F7/49994 ,  G06F9/30029

摘要： Neural processing elements are configured with a hardware AND gate configured to perform a logical AND operation between a sign extend signal and a most significant bit (“MSB”) of an operand. The state of the sign extend signal can be based upon a type of a layer of a deep neural network (“DNN”) that generate the operand. If the sign extend signal is logical FALSE, no sign extension is performed. If the sign extend signal is logical TRUE, a concatenator concatenates the output of the hardware AND gate and the operand, thereby extending the operand from an N-bit unsigned binary value to an N+1 bit signed binary value. The neural processing element can also include another hardware AND gate and another concatenator for processing another operand similarly. The outputs of the concatenators for both operands are provided to a hardware binary multiplier.

公开(公告)号：US20230185531A1

公开(公告)日：2023-06-15

申请号：US18080673

申请日：2022-12-13

申请人： Flex Logix Technologies, Inc.

发明人： Frederick A. Ware ,  Cheng C. Wang

IPC分类号： G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  G06F9/54

CPC分类号： G06F7/5443 ,  G06F7/523 ,  G06F7/50 ,  G06F9/542

摘要： Multiply-accumulate processors within a tensor processing unit simultaneously execute, in each of a sequence of multiply-accumulate cycles, respective multiply operations using a shared input data operand and respective weighting operands, each of the multiply-accumulate processors applying a new shared input data operand and respective weighting operand in each successive multiply-accumulate cycle to accumulate, as a component of an output tensor, a respective sum-of-multiplication-products.

公开(公告)号：US11675624B2

公开(公告)日：2023-06-13

申请号：US16833610

申请日：2020-03-29

申请人： Micron Technology, Inc.

发明人： Aliasger Zaidy ,  Andre Xian Ming Chang ,  Eugenio Culurciello

IPC分类号： G06F7/50 ,  G06F9/50 ,  G06F7/523 ,  G06F9/30 ,  G06F9/54 ,  G06N3/063

CPC分类号： G06F9/5027 ,  G06F7/50 ,  G06F7/523 ,  G06F9/30098 ,  G06F9/544 ,  G06N3/063

摘要： An inference engine circuit architecture is disclosed which includes a matrix-matrix (MM) processor circuit and a MM accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative MM accelerator circuit includes a first buffer circuit storing maps data; a first data network; multiple second buffer circuits each storing different kernel data; multiple second, serial data networks, with each coupled to a corresponding second buffer circuit; and a plurality of vector-vector (VV) acceleration circuits arranged in a plurality of arrays. Each VV acceleration circuit includes multiply and accumulate circuits; a shift register; a control multiplexer to provide a selected output, in response to a mode control word, of a bias parameter or a first accumulation sum; and a second adder circuit which adds the multiplicative product to the bias parameter or to the first accumulation sum to generate a second or next accumulation sum.

公开(公告)号：US20230169144A1

公开(公告)日：2023-06-01

申请号：US17920372

申请日：2021-02-08

申请人： Cambricon (Xi'an) Semiconductor Co., Ltd.

发明人： Shaoli LIU ,  Deyuan HE ,  Daofu LIU

IPC分类号： G06F17/16 ,  G06F7/523 ,  G06F7/544 ,  G06F7/50

CPC分类号： G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G06F7/5443

摘要： The present disclosure relates to an operation method, a processor, and related products that improve operation efficiency during matrix multiplication. The products include a storage component, an interface apparatus, a control component, and the an artificial intelligence chip. The artificial intelligence chip is connected to the storage component, the control component, and the interface apparatus, respectively. The storage component stores data. The interface apparatus implements data transfer between the artificial intelligence chip and an external device. The control component monitors a state of the artificial intelligence chip. .

公开(公告)号：US11664070B2

公开(公告)日：2023-05-30

申请号：US17344555

申请日：2021-06-10

申请人： MACRONIX International Co., Ltd.

发明人： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC分类号： G11C11/4093 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06F7/523 ,  G06F7/501

CPC分类号： G11C11/4093 ,  G06F7/501 ,  G06F7/523 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

摘要： An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

公开(公告)号：US20230153265A1

公开(公告)日：2023-05-18

申请号：US18092247

申请日：2022-12-31

申请人： Cornami, Inc.

发明人： Paul L. Master ,  Steven K. Knapp ,  Raymond J. Andraka ,  Alexei Beliaev ,  Martin A. Franz ,  Rene Meessen ,  Frederick Curtis Furtek

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F7/52 ,  G06F5/01 ,  G06F9/48 ,  G06F7/50 ,  G06F7/544 ,  H03K19/21 ,  G06F7/523 ,  G06F7/487

CPC分类号： G06F15/80 ,  G06F9/30098 ,  G06F9/3855 ,  G06F9/54 ,  G06F7/52 ,  G06F5/01 ,  G06F9/4881 ,  G06F7/50 ,  G06F7/5443 ,  H03K19/21 ,  G06F7/523 ,  G06F7/487 ,  G06F2207/382

摘要： A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

公开(公告)号：US20230153068A1

公开(公告)日：2023-05-18

申请号：US17425216

申请日：2021-07-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Bumkwi CHOI ,  Daesung LIM ,  Sunbum HAN

IPC分类号： G06F7/523 ,  G06F5/01

CPC分类号： G06F7/523 ,  G06F5/01

摘要： An electronic apparatus is provided. The electronic apparatus includes: an input interface; a memory configured to store a plurality of weights corresponding to an artificial intelligence model; and a processor configured to perform a neural network computation with respect to input data provided through the input interface based on the plurality of weights. The processor is also configured to, based on any one or any combination of the input data, the plurality of weights, and a computation result obtained in a process of performing the neural network computation being within a threshold range, change an original value within the threshold range to a preset value and perform the neural network computation based on the preset value.

公开(公告)号：US20230131035A1

公开(公告)日：2023-04-27

申请号：US18085939

申请日：2022-12-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungju RYU ,  Hyungjun KIM ,  Jae-Joon KIM

IPC分类号： G06N3/063 ,  G06F7/485 ,  G06F7/523

摘要： Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

公开(公告)号：US11635942B2

公开(公告)日：2023-04-25

申请号：US17407540

申请日：2021-08-20

申请人： SK hynix Inc.

发明人： Jeong Jun Lee

IPC分类号： G06F7/544 ,  G06F7/523 ,  G06F7/501

摘要： A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

公开(公告)号：US20230097158A1

公开(公告)日：2023-03-30

申请号：US17548575

申请日：2021-12-12

申请人： Skymizer Taiwan Inc.

发明人： Wen Li Tang ,  Shu-Ming Liu ,  Der-Yu Tsai ,  Po-Sheng Chang

IPC分类号： H03M1/10 ,  G06F7/501 ,  G06F7/523 ,  G06N3/063

摘要： An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.