公开(公告)号：USRE35125E

公开(公告)日：1995-12-19

申请号：US212722

申请日：1994-03-14

申请人： Yuji Kaneko

发明人： Yuji Kaneko

IPC分类号： B23H1/02 ,  B23H7/04 ,  H03K19/02

CPC分类号： B23H1/022

摘要： This invention provides a a ROM (10) which stores circuit function definition data for defining specified logic circuits relating to electric discharge machining and a programmable IC (20) which defines a specified logic circuit according to the circuit function definition data. This configuration is cost effective and minimizes hardware space requirements compared with configurations which used different logic circuits combined together. Further, when hardware needs to be reconfigured, the change can be achieved easily by replacing ROM (10) only.

摘要翻译： 本发明提供了一种ROM（10），其存储用于定义与放电加工相关的指定逻辑电路的电路功能定义数据和根据电路功能定义数据定义指定逻辑电路的可编程IC（20）。 与使用不同逻辑电路组合在一起的配置相比，该配置具有成本效益并最大限度地减少了硬件空间需求。 此外，当需要重新配置硬件时，只需更换ROM（10）即可轻松实现更改。

公开(公告)号：US5457413A

公开(公告)日：1995-10-10

申请号：US130661

申请日：1993-10-01

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02

CPC分类号： H03K19/09448 ,  H03K19/013

摘要： A BiMIS circuit has first and second input terminals; first and second output terminals; a first bipolar transistor having a collector receiving a first potential, an emitter connected to the first output terminal, and a base connected to the second output terminal; a second bipolar transistor having a collector connected to the first output terminal and an emitter receiving a reference potential; a first MIS transistor circuit including MIS transistors, connected to the base and the collector of the first bipolar transistor and the first input terminal, and turned on or off depending on a potential of the first input terminal; and a second MIS transistor circuit including MIS transistors, connected to the base of the first bipolar transistor, the second input terminal and the base of the second bipolar transistor, and turned on or off depending on a potential of the second input terminal. The BiMIS circuit includes at least one of: a capacitor having one terminal connected to the first input terminal and the other terminal connected to the base of the second bipolar transistor; a discharging circuit connected to the base of the first bipolar transistor for discharging the base; and a potential setting circuit connected to the base of the second bipolar transistor for setting a potential of the base at a predetermined level.

摘要翻译： BiMIS电路具有第一和第二输入端; 第一和第二输出端子; 具有接收第一电位的集电极的第一双极晶体管，连接到第一输出端子的发射极和连接到第二输出端子的基极; 第二双极晶体管，其具有连接到第一输出端子的集电极和接收参考电位的发射极; 包括MIS晶体管的第一MIS晶体管电路，连接到第一双极晶体管的基极和集电极以及第一输入端，并根据第一输入端的电位导通或截止; 以及第二MIS晶体管电路，其包括连接到第一双极晶体管的基极，第二输入端子和第二双极晶体管的基极的MIS晶体管，并且根据第二输入端子的电位而导通或截止。 BiMIS电路包括以下至少一个：具有连接到第一输入端子的一个端子和连接到第二双极晶体管的基极的另一个端子的电容器; 放电电路，连接到第一双极晶体管的基极，用于对基极进行放电; 以及电位设定电路，连接到第二双极晶体管的基极，用于将基极的电位设定在预定电平。

公开(公告)号：US5399918A

公开(公告)日：1995-03-21

申请号：US129664

申请日：1993-09-30

申请人： Gregory F. Taylor ,  Lawrence T. Clark

发明人： Gregory F. Taylor ,  Lawrence T. Clark

IPC分类号： G06F15/78 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/16

CPC分类号： H03K19/00346 ,  H03K19/09448

摘要： A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.

摘要翻译： 高可靠性，大型风扇，高速BiCMOS电路。 通过向基本逻辑电路的每个输入添加双极晶体管的发射极电容，减少了出现在电路的输出线上的MOS晶体管寄生电容的量。 提供电路以提高反向偏置双极晶体管的基极电压，以减少或消除反向偏置。

公开(公告)号：US5338987A

公开(公告)日：1994-08-16

申请号：US150741

申请日：1993-11-12

申请人： Stephen R. Tomasetti ,  Danny Tsong

发明人： Stephen R. Tomasetti ,  Danny Tsong

IPC分类号： H03K17/567 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H04B1/40 ,  H03K3/01 ,  H03K19/02

CPC分类号： H03K19/017518

摘要： A BiCMOS output driver for a transceiver circuit has a pull-up/pull-down circuit with CMOS transistors supplying base current to bipolar pull-up/pull-down transistors. In its quiescent state, the CMOS transistors draw no current. A current mirror circuit comprising a pair of bipolar transistors sized to be a fraction of the pull-up/pull-down transistors is coupled between the input and output of the pull-up/pull-down circuit to prevent exceeding a predetermined current. A speed up circuit comprising CMOS transistors coupled between ground and the base of the bipolar pull-up/pull-down transistors to speed up the shut off of the transistors.

摘要翻译： 用于收发器电路的BiCMOS输出驱动器具有上拉/下拉电路，CMOS晶体管为双极上拉/下拉晶体管提供基极电流。 在静态状态下，CMOS晶体管不产生电流。 包括一对双极晶体管的电流镜电路，其尺寸设置为上拉/下拉晶体管的一部分，被耦合在上拉/下拉电路的输入和输出之间以防止超过预定电流。 一种加速电路，其包括耦合在双极上拉/下拉晶体管的地和基极之间的CMOS晶体管，以加速晶体管的截止。

公开(公告)号：US5311078A

公开(公告)日：1994-05-10

申请号：US878615

申请日：1992-05-05

申请人： Hiroshi Makino ,  Yasunobu Nakase ,  Kimio Ueda

发明人： Hiroshi Makino ,  Yasunobu Nakase ,  Kimio Ueda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K19/013 ,  H03K19/0944 ,  H01L29/78 ,  H01L29/02 ,  H03K19/02 ,  H03K19/08

CPC分类号： H03K19/09448 ,  H01L27/0623 ,  H03K19/0136

摘要： In order to obtain a logic circuit capable of performing a high-speed operation, respective gates of a P-channel MOSFET (1) and an N-channel MOSFET (2) are connected to an input node (6) in common, and ends of resistors (12, 13) are connected to respective drains thereof. Respective emitters of an NPN transistor (3) and a PNP transistor (4) are connected to an output node (9) with an end of a resistor (5) in common, and ends of the resistors (12, 13) are connected to respective bases thereof. A source of the P-channel MOSFET (1) and a collector of the NPN transistor (3) are connected to a high potential point (8) in common while a source of the N-channel MOSFET (2) and a collector of the PNP transistor (4) are connected to a low potential point (40) in common respectively. Respective other ends of the resistors (5, 12, 13) are connected at a node (7) in common. Thus, the potential of an output terminal quickly fluctuates when a bipolar transistor is in an ON state.

摘要翻译： 为了获得能够执行高速操作的逻辑电路，P沟道MOSFET（1）和N沟道MOSFET（2）的各个栅极共同地连接到输入节点（6），并且结束 的电阻器（12,13）连接到其各自的漏极。 NPN晶体管（3）和PNP晶体管（4）的各个发射极与电阻器（5）的端部共同连接到输出节点（9），并且电阻器（12,13）的端部连接到 各自的碱基。 P沟道MOSFET（1）的源极和NPN晶体管（3）的集电极共同连接到高电位点（8），而N沟道MOSFET（2）的源极和 PNP晶体管（4）分别连接到低电位点（40）。 电阻器（5,12,13）的各个另一端在节点（7）处共同连接。 因此，当双极晶体管处于导通状态时，输出端子的电位迅速波动。

公开(公告)号：US5302870A

公开(公告)日：1994-04-12

申请号：US001429

申请日：1993-01-06

申请人： Wen-Foo Chern

发明人： Wen-Foo Chern

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H03F3/45 ,  H03K19/02

CPC分类号： G11C11/4091 ,  G11C7/06

摘要： A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage. The initial momentary discharge of the sense node to the first potential allows a sense amplifier to behave like a conventional sense amplifier during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground. Decreasing the second potential to a third potential at the initiation of the precharge cycle effects a decrease in the equilibrate potential of the digit lines, thereby increasing the "high logic window" as reflected in an increase in cell margin and a decrease in soft error rate (SER).

摘要翻译： 一种多电平电位产生电路，通过首先使节点接地到等于参考电位的第一电位，将感测节点带到三个电位，然后使节点浮动到等于参考电位的基本稳定的第二电位加上等于参考电位的阈值电压 通过漏电流泵送的电气装置。 然后将第二电位降低到大于或等于第一电位的第三电势。 这里描述的电压感测通常用于在DRAM周期的有效部分期间以及在DRAM周期的预充电部分的启动期间偏置动态随机存取存储器（DRAM）器件中的数字线。 第二电位减小了存储单元的电流泄漏，而不利用具有高阈值电压的电气装置。 感测节点到初始电位的初始瞬时放电允许读出放大器在初始感测期间像传统的读出放大器一样，从而允许最小数字/数字*感测电位近似接近。 在预充电循环开始时，将第二电势降低到第三电位，使得数字线的平衡电位降低，从而增加“高逻辑窗”，反映在单元余量的增加和软错误率的降低 （SER）。

公开(公告)号：US5280196A

公开(公告)日：1994-01-18

申请号：US42940

申请日：1993-04-05

申请人： Eiji Shinozaki

发明人： Eiji Shinozaki

IPC分类号： G11B5/09 ,  H03K17/567 ,  H03K3/01 ,  H03K19/02

CPC分类号： H03K17/567 ,  G11B5/09

摘要： A magnetic head drive circuit includes a first MOS transistor of a first conductivity type, a bipolar transistor of a second conductivity type, a second MOS transistor of the second conductivity type, a second bipolar transistor of the first conductivity type. The first MOS transistor of a first conductivity type has a source connected to a first power supply. The first bipolar transistor of a second conductivity type is connected in series with the first MOS transistor and has a common node thereof as a first output terminal, an emitter connected to a second power supply, and a collector current controlled as a constant current. The second MOS transistor of the second conductivity type has a source connected to the first power supply. The second bipolar transistor of the first conductivity type is connected in series with the second MOS transistor and has a common node thereof as a second output terminal, an emitter connected to the second power supply, and a collector current controlled as a constant current.

摘要翻译： 磁头驱动电路包括第一导电类型的第一MOS晶体管，第二导电类型的双极晶体管，第二导电类型的第二MOS晶体管，第一导电类型的第二双极晶体管。 第一导电类型的第一MOS晶体管具有连接到第一电源的源极。 第二导电类型的第一双极晶体管与第一MOS晶体管串联连接，并具有作为第一输出端的公共节点，连接到第二电源的发射极和作为恒定电流控制的集电极电流。 第二导电类型的第二MOS晶体管具有连接到第一电源的源极。 第一导电类型的第二双极晶体管与第二MOS晶体管串联连接，并具有作为第二输出端的公共节点，连接到第二电源的发射极和作为恒定电流控制的集电极电流。

公开(公告)号：US5270588A

公开(公告)日：1993-12-14

申请号：US813451

申请日：1991-12-26

申请人： Yun-ho Choi

发明人： Yun-ho Choi

IPC分类号： G11C7/10 ,  H03K19/017 ,  H03K19/092 ,  H03K19/02

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  H03K19/01714 ,  H03K19/01721

摘要： A data output buffer includes an output driving stage having a pair of parallel pull-up transistors and a pull-down transistor, a latch circuit for latching a pair of complementary signals, a second gate for gating the non-inverted output signal of the latch circuit in response to an external output enable signal and then supplying it to the gate of one pull-up transistor of the output driving state, a third gate also for gating the non-inverted output signal of the latch circuit in response to an external output enable signal, and a selective bootstrap circuit for driving the other pull-up transistor of the output driving stage. The output driving stage is driven to an external supply voltage when the external supply voltage is higher than a set voltage, and is driven to a boosted voltage when the external supply voltage is lower than the set voltage, determined by output signals from the second and third gates.

摘要翻译： 数据输出缓冲器包括具有一对并行上拉晶体管和下拉晶体管的输出驱动级，用于锁存一对互补信号的锁存电路，用于选通锁存器的非反相输出信号的第二门 电路，响应于外部输出使能信号，然后将其提供给输出驱动状态的一个上拉晶体管的栅极，第三栅极还用于响应于外部输出门控锁存电路的非反相输出信号 使能信号和用于驱动输出驱动级的另一个上拉晶体管的选择性自举电路。 当外部电源电压高于设定电压时，输出驱动级被驱动到外部电源电压，并且当外部电源电压低于由第二和第二输出信号确定的设定电压时被驱动到升压电压 第三门。

公开(公告)号：US4808853A

公开(公告)日：1989-02-28

申请号：US125272

申请日：1987-11-25

申请人： Stewart S. Taylor

发明人： Stewart S. Taylor

IPC分类号： H03K19/00 ,  H03K19/094 ,  H03K17/16 ,  H03K19/02

CPC分类号： H03K19/0005 ,  H03K19/09429

摘要： A tristate output circuit includes a pair of transistors having sources connected to a switchable current source and drains separately coupled to a voltage source through separate resistors and switching transistors. When the current source and switching transistors are on, the circuit operates in a back termination mode wherein it amplifies a differential input signal applied across the gates of the transistor pair to produce a differential output signal across their drains for transmission on a transmission line. The load resistors are sized to match the characteristic impedance of a transmission line so as to properly terminate the transmission line. In an open drain mode, the switching transistors are off, uncoupling the drains of the transistor pair from the voltage source so as to increase output impedance. In a tristate mode, the current source and switching transistors are turned off, thereby turning off the transistor pair and rendering the output impedance of the circuit substantially infinite.

摘要翻译： 三态输出电路包括一对晶体管，其具有连接到可切换电流源的源极，并且通过单独的电阻器和开关晶体管分别耦合到电压源的漏极。 当电流源和开关晶体管导通时，电路工作在后端模式，其中放大施加在晶体管对的栅极上的差分输入信号，以在其漏极之间产生差分输出信号，以在传输线上传输。 负载电阻的大小与传输线的特性阻抗相匹配，以适当地终止传输线。 在开漏模式中，开关晶体管断开，使晶体管对的漏极与电压源分离，从而增加输出阻抗。 在三态模式中，电流源和开关晶体管截止，从而关断晶体管对，并使电路的输出阻抗基本上无限大。

公开(公告)号：US4794280A

公开(公告)日：1988-12-27

申请号：US158004

申请日：1988-02-16

申请人： Hiep Van Tran

发明人： Hiep Van Tran

IPC分类号： H03K17/04 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K3/26 ,  H03K17/60 ,  H03K17/687

CPC分类号： H03K19/09448 ,  H03K19/0133 ,  H03K19/0136

摘要： A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resistive circuitry which allow bootstrapped voltages.

摘要翻译： 提供了一种驱动器电路，其提供降低的输入负载，增加的输出负载以及对应于逻辑1的高电压输出电平。 这些结果通过使用允许自举电压的上拉晶体管和电容和电阻电路来实现。