公开(公告)号：US20200004691A1

公开(公告)日：2020-01-02

申请号：US16570700

申请日：2019-09-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jani Kokkonen

IPC: G06F12/1036 ,  G06F12/109 ,  G06F9/455 ,  G06F13/16

Abstract: An apparatus for managing a dynamic random access memory (DRAM) includes a processor configured to map a plurality of clusters of banks of the DRAM to a plurality of applications executing on a common virtual machine (VM), where the common VM runs on a host operating system (OS) of a host computing device, and where each of the clusters of banks is used exclusively by each mapped application.

公开(公告)号：US20190384723A1

公开(公告)日：2019-12-19

申请号：US16474551

申请日：2017-12-28

Applicant: BULL SAS

Inventor： Francois WELLENREITER

IPC: G06F12/1036 ,  G06F12/1081 ,  G06F12/02

Abstract: Disclosed is a method for managing, in a computer system including a peripheral device and its driver, a virtual memory of a using application of the peripheral device which can access the virtual memory of the using application, the management method including: the creation, in the virtual memory of the using application, of a virtual memory pool which is accessible to the peripheral device but inaccessible to the using application; and the creation of a management application that is separate from the using application and is dedicated to the allocation of at least this virtual memory pool and to the releasing of at least this virtual memory pool.

公开(公告)号：US10447712B2

公开(公告)日：2019-10-15

申请号：US15449042

申请日：2017-03-03

Applicant: Palantir Technologies Inc.

Inventor： Alexander Visbal ,  James Thompson ,  Marvin Sum ,  Jason Ma ,  Bing Jie Fu ,  Ilya Nepomnyashchiy ,  Devin Witherspoon ,  Victoria Lai ,  Steven Berler ,  Alexei Smaliy ,  Suchan Lee

IPC: G06Q40/00 ,  H04L29/06 ,  G06F16/28 ,  G06F16/9038 ,  G06F16/2457 ,  G06F3/0482 ,  G06F3/0484 ,  G06Q40/02 ,  G06F12/1036 ,  G06K9/62 ,  G06F16/34 ,  G06F21/55

Abstract: Embodiments of the present disclosure relate to a data analysis system that may automatically generate memory-efficient clustered data structures, automatically analyze those clustered data structures, automatically tag and group those clustered data structures, and provide results of the automated analysis and grouping in an optimized way to an analyst. The automated analysis of the clustered data structures (also referred to herein as data clusters) may include an automated application of various criteria or rules so as to generate a tiled display of the groups of related data clusters such that the analyst may quickly and efficiently evaluate the groups of data clusters. In particular, the groups of data clusters may be dynamically re-grouped and/or filtered in an interactive user interface so as to enable an analyst to quickly navigate among information associated with various groups of data clusters and efficiently evaluate those data clusters in the context of, for example, a fraud investigation.

公开(公告)号：US10423539B2

公开(公告)日：2019-09-24

申请号：US15830160

申请日：2017-12-04

Applicant: International Business Machines Corporation

Inventor： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/02 ,  G06F12/1036 ,  G06F9/30 ,  G06F13/00 ,  G06F13/28

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10379785B2

公开(公告)日：2019-08-13

申请号：US15153624

申请日：2016-05-12

Applicant: Cryptography Research, Inc.

Inventor： Ambuj Kumar ,  Roy Moss

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/1036

Abstract: A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (OTP) memory of a device. Furthermore, a second virtual address of the virtual memory may be mapped to a second physical address of a static memory of the device. The virtual memory that is mapped to the OTP memory and the static memory may be provided for accessing of the data of the OTP memory of the device.

公开(公告)号：US20190227947A1

公开(公告)日：2019-07-25

申请号：US16370848

申请日：2019-03-29

Applicant: David Pardo Keppel ,  Binh Pham

Inventor： David Pardo Keppel ,  Binh Pham

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/1045

Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

公开(公告)号：US10324859B2

公开(公告)日：2019-06-18

申请号：US15633388

申请日：2017-06-26

Applicant: Western Digital Technologies, Inc.

Inventor： Daniel Joseph Linnen ,  Ashish Ghai ,  Dongxiang Liao ,  Srikar Peesari ,  Avinash Rajagiri ,  Philip Reusswig ,  Bin Wu

IPC: G06F12/10 ,  G06F12/1036 ,  G06F3/06 ,  G06F11/10 ,  G06F11/14

Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

公开(公告)号：US20190121745A1

公开(公告)日：2019-04-25

申请号：US15789861

申请日：2017-10-20

Applicant: Microsoft Technology Licensing, LLC

Inventor： Hadden Mark Hoppert

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

Abstract: Embodiments relate to removing, or replacing with an emulator, a physical hardware device that backs a virtual device of a virtual machine (VM), and doing so while the VM and a guest operating system therein remain live and continue executing. In the case of removing the physical hardware device, the physical hardware device stops backing the virtual hardware device while the guest operating system continues to execute and have access to the virtual device. Disruption of the guest operating system may be avoided using techniques described herein. In the case of replacing the physical hardware device with an emulator, the emulator serves as a placeholder for the physical hardware device and allows the guest operating system to continue interacting with the virtual device without degradation of functionality. Removal of the physical hardware device and/or remapping the virtual device to an emulator may be transparent to the guest operating system.

公开(公告)号：US10241795B2

公开(公告)日：2019-03-26

申请号：US15208404

申请日：2016-07-12

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/355 ,  G06F12/1036 ,  G06F9/455 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0895 ,  G06F12/0897

Abstract: A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.