公开(公告)号：US11527570B2

公开(公告)日：2022-12-13

申请号：US17199779

申请日：2021-03-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/148 ,  H04N5/372 ,  H01L27/146

Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

公开(公告)号：US11454669B2

公开(公告)日：2022-09-27

申请号：US16680114

申请日：2019-11-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Manoj Kumar ,  Lionel Courau ,  Geeta ,  Olivier Le-Briz

IPC: G01R31/28 ,  H05K1/02 ,  H01L21/66 ,  H01L23/525

Abstract: An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.

公开(公告)号：US11417789B2

公开(公告)日：2022-08-16

申请号：US16825298

申请日：2020-03-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud Tournier ,  Boris Rodrigues Goncalves ,  Francois Roy

IPC: H01L31/107 ,  H01L27/146

Abstract: An electronic device is provided that includes a photodiode. The photodiode includes a semiconductor region coupled to a node of application of a first voltage, and at least one semiconductor wall. The at least one semiconductor wall extends along at least a height of the photodiode and partially surrounds the semiconductor region.

公开(公告)号：US20220231483A1

公开(公告)日：2022-07-21

申请号：US17715509

申请日：2022-04-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mathias PROST ,  Moustafa EL KURDI ,  Philippe BOUCAUD ,  Frederic BOEUF

IPC: H01S5/32 ,  H01S5/02 ,  H01S5/042 ,  H01S5/227 ,  H01S5/30 ,  H01S5/10

Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.

公开(公告)号：US11329067B2

公开(公告)日：2022-05-10

申请号：US16898700

申请日：2020-06-11

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Jacques Fagot ,  Philippe Boivin ,  Franck Arnaud

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/808 ,  H01L21/84 ,  H01L27/06

Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

公开(公告)号：US20220131246A1

公开(公告)日：2022-04-28

申请号：US17646964

申请日：2022-01-04

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Victor Fiorese ,  Frederic Gianesello ,  Florian Voineau

IPC: H01P1/161 ,  H01P1/213 ,  H01P5/19 ,  H01Q25/00

Abstract: An orthomode junction for separating and/or combining orthogonally-polarized radiofrequency wave signals, comprises a body which has a main cavity forming a main waveguide, which has a blind end, and auxiliary cavities forming auxiliary waveguides, which communicate laterally with the main cavity in the vicinity of the blind end thereof, and a deflection insert situated at the blind end of the main cavity and facing the auxiliary cavities, the deflection insert having different shapes on the side of the auxiliary cavities respectively.

公开(公告)号：US20220115419A1

公开(公告)日：2022-04-14

申请号：US17498286

申请日：2021-10-11

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Francois GUYADER ,  Sara PELLEGRINI ,  Bruce RAE

IPC: H01L27/146 ,  H01L31/107 ,  H04N5/369 ,  G01J1/44

Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

公开(公告)号：US20220028725A1

公开(公告)日：2022-01-27

申请号：US17496411

申请日：2021-10-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal GOURAUD ,  Delia RISTOIU

IPC: H01L21/762 ,  H01L29/06

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

公开(公告)号：US20220020924A1

公开(公告)日：2022-01-20

申请号：US17488026

申请日：2021-09-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Yann CANVEL ,  Sebastien LAGRASTA ,  Sebastien BARNOLA ,  Christelle BOIXADERAS

IPC: H01L45/00

Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

公开(公告)号：US11212475B2

公开(公告)日：2021-12-28

申请号：US16890944

申请日：2020-06-02

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Laurent Simony ,  Pierre Malinge

IPC: H04N5/374 ,  H04N5/341 ,  H04N5/355

Abstract: A sensor includes pixels each including: a first transistor and a first switch in series between a first node and an internal node of the pixel, a gate of the first transistor being coupled to a second node; a capacitive element, a first terminal of which is connected to the second node; and a plurality of assemblies each including a capacitance in series with a second switch coupled to the internal node. The sensor includes a circuit configured to control, each time a voltage is stored in one of the assemblies, the interruption of a current between the first node and the internal node: by switching a first potential applied to a second terminal of the capacitive element; or by opening the first switch.