公开(公告)号：US6118717A

公开(公告)日：2000-09-12

申请号：US354401

申请日：1999-07-15

Applicant: James Brady

Inventor： James Brady

IPC: G11C11/417 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C7/1006 ,  G11C7/12 ,  G11C2207/104

Abstract: A device for directly loading data onto bit lines of DRAMs. The device eliminates the need for performing a read cycle prior to a write cycle by bypassing the sense amplifiers of the DRAM. An I/O data line is connected to a bit line by a first transmission gate. A second transmission gate is electrically connected between the first transmission gate and the sense amplifier. A voltage level representing a data bit is loaded directly onto a bit line by turning off the second transmission gate to isolate the sense amplifier from the bit line and turning on the first transmission gate to connect the data line to the bit line. The voltage level on the bit line is then stored in a memory cell connected to the bit line.

Abstract translation: 用于将数据直接加载到DRAM的位线的装置。 器件消除了通过绕过DRAM的读出放大器在写周期之前执行读周期的需要。 I / O数据线通过第一传输门连接到位线。 第二传输门电连接在第一传输门和读出放大器之间。 表示数据位的电压电平通过关闭第二传输门直接加载到位线上，以使读出放大器与位线隔离，并接通第一传输门以将数据线连接到位线。 然后将位线上的电压电平存储在连接到位线的存储单元中。

公开(公告)号：US6101618A

公开(公告)日：2000-08-08

申请号：US172848

申请日：1993-12-22

Applicant: David Charles McClure

Inventor： David Charles McClure

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  H02H3/05

CPC classification number: G11C29/835 ,  G11C29/02 ,  G11C29/44 ,  G11C2029/0403

Abstract: A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.

Abstract translation: 用于测试封装的半导体存储器件的方法和电路允许通过在封装的存储器芯片上执行三个可能的冗余卷积测试之一来获取关于冗余元件的信息。 通过刺激封装器件的引脚，存储器芯片被设置为三种测试模式之一。 在第一测试模式中，感测到指示冗余的预置信号，并且输出引脚的状态改变。 在第二测试模式中，当冗余行被寻址时，存储器阵列行被顺序寻址并且输出引脚的状态被改变。 在第三个测试中，顺序寻址阵列列，并且当冗余列被寻址时，更改冗余列映射到的输出引脚的状态。

公开(公告)号：US6100194A

公开(公告)日：2000-08-08

申请号：US102431

申请日：1998-06-22

Applicant: Tsiu C. Chan ,  Anthony M. Chiu ,  Gregory C. Smith

Inventor： Tsiu C. Chan ,  Anthony M. Chiu ,  Gregory C. Smith

IPC: C23C18/31 ,  C25D3/46 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1089 ,  H01L2924/0002

Abstract: Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 .mu.m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver and other layers above the insulating material are then removed by chemical-mechanical polishing, leaving a silver interconnect connected to the exposed portion of the contact region; and extending over adjacent insulating regions to another contact region or a bond pad. Silver interconnects thus formed may have smaller cross-sections, and thus a greater density in a given area, than conventional metallic interconnects.

Abstract translation: 通过在接触区域上将深槽蚀刻成绝缘层，暴露接触区域的部分并限定互连形成银互连。 蚀刻具有截断的V形或U形的凹槽，在顶部比在任何其它垂直位置处更宽，并且具有0.25μm或更小的最小宽度。 将可选的粘合层和阻挡层溅射到包括侧壁的凹槽的表面上，然后溅射沉积种子层。 当铝用作种子层时，可以任选地使用锌化工艺以促进银与种子层的粘附。 然后通过在银溶液中电镀银，或者通过在铜溶液中电镀银和铜，然后在银溶液中电镀来填充槽。 导致的填充凹槽通常不会由金属溅射沉积到这样窄的深沟槽中而产生空隙，尽管接缝可以间歇地存在于填充凹槽的部分中，其中从相对的侧壁电镀的金属在 收敛。 然后通过化学机械抛光去除绝缘材料上方的银和其它层的部分，留下连接到接触区域的暴露部分的银互连; 并且在相邻的绝缘区域上延伸到另一个接触区域或接合焊盘。 如此形成的银互连可以具有比常规金属互连更小的横截面，并且因此在给定区域中具有更大的密度。

公开(公告)号：US6094026A

公开(公告)日：2000-07-25

申请号：US191060

申请日：1994-02-02

Applicant: Scott W. Cameron

Inventor： Scott W. Cameron

IPC: G08B21/00 ,  H02H5/04 ,  H02H7/08 ,  H02H7/085 ,  H02P6/00 ,  H02P6/08 ,  H02P6/12 ,  H02P1/04

CPC classification number: H02H7/0833 ,  H02P6/085 ,  H02P6/34 ,  H02H5/044 ,  H02H7/0858

Abstract: A method and integrated circuit for providing drive signals to a polyphase dc motor. The integrated circuit is fabricated on a semiconductor substrate for providing drive signals to a polyphase dc motor. The circuit includes a coil drive circuit for connection to drive coils of the motor to selectively supply drive currents thereto in a predetermined sequence. A sequencer circuit commutatively selects the drive coils to which the drive currents are selectively supplied, and a motor, speed controlling circuit controls the speed of the motor by controlling the speed of commutation. A temperature sensing element, such as a diode, is fabricated in the substrate to indicate the temperature of the substrate, and a temperature measuring circuit is connected to the temperature sensing element and to the motor speed controlling circuit to operate the motor speed controlling circuit to slow the speed of the motor when the temperature of the substrate exceeds a first predetermined temperature. If desired, temperature measuring circuit can include a circuit for measuring a second temperature higher than the first predetermined temperature to operate a shut down circuit to turn off the motor if the substrate temperature is too high.

Abstract translation: 一种用于向多相直流电动机提供驱动信号的方法和集成电路。 集成电路制造在半导体衬底上，用于向多相直流电动机提供驱动信号。 该电路包括用于连接到电动机的驱动线圈的线圈驱动电路，以预定的顺序选择性地提供驱动电流。 定序器电路对选择性地提供驱动电流的驱动线圈进行换相选择，电动机，速度控制电路通过控制换向速度来控制电动机的转速。 在衬底中制造诸如二极管的温度感测元件以指示衬底的温度，并且温度测量电路连接到温度感测元件和电动机速度控制电路，以将电动机速度控制电路操作为 当基板的温度超过第一预定温度时，减慢马达的速度。 如果需要，温度测量电路可以包括用于测量高于第一预定温度的第二温度的电路，以便如果衬底温度太高，则操作关闭电路以关闭电动机。

公开(公告)号：US6087697A

公开(公告)日：2000-07-11

申请号：US962342

申请日：1997-10-31

Applicant: Viren C. Patel

Inventor： Viren C. Patel

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/42376 ,  H01L29/7802 ,  Y10S438/931

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance C.sub.gd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract translation: 公开了适用于RF应用的功率MOSFET及其制造方法。 功率MOSFET降低了器件漏极区域的栅极覆盖范围，以便将器件栅极降低到漏极电容Cgd。 通过去除设置在位于器件的主体区域的沟道部分之间的漏极区域的基本部分上的多晶硅层的一部分来消除覆盖漏极区域的栅极的重要部分。 产生的开放区域随后被氧化物层覆盖，分离器件的多晶硅栅电极。 最后，在整个结构上沉积金属层以形成器件的栅极和源极。

公开(公告)号：US6086244A

公开(公告)日：2000-07-11

申请号：US822601

申请日：1997-03-20

Applicant: Rong Yin

Inventor： Rong Yin

IPC: G04G3/02 ,  G04C19/02

CPC classification number: G04G3/02

Abstract: A temperature compensated clock and method of clocking systems are provided. The clock preferably has an oscillator for generating an oscillating waveform signal at a preselected frequency and a frequency divider responsive to the oscillator for dividing the frequency of the oscillating waveform signal. A temperature monitoring circuit is positioned responsive to a voltage input signal independent of temperature and a voltage input signal proportional to temperature for monitoring temperature variations. A temperature compensating circuit, preferably including a programmable scaling circuit, is responsive to the frequency divider and the temperature monitoring circuit for scaling the divided frequency of the generated waveform and thereby advantageously produces a temperature compensated output timing signal.

Abstract translation: 提供了温度补偿时钟和计时系统的方法。 时钟优选地具有用于以预选频率产生振荡波形信号的振荡器和响应于振荡器分频振荡波形信号的频率的分频器。 温度监测电路响应于独立于温度的电压输入信号和与温度成比例的电压输入信号来定位，用于监测温度变化。 优选地包括可编程缩放电路的温度补偿电路响应于分频器和温度监视电路，用于缩放产生的波形的分频，从而有利地产生温度补偿的输出定时信号。

公开(公告)号：US6084267A

公开(公告)日：2000-07-04

申请号：US168572

申请日：1998-10-08

Applicant: Gianluca Petrosino

Inventor： Gianluca Petrosino

IPC: G01R31/28 ,  H01L23/544 ,  H01L31/062 ,  H01L29/76 ,  H01L31/113

CPC classification number: H01L22/34 ,  G01R31/2853 ,  H01L2924/0002

Abstract: A semiconductor integrated circuit comprises a substrate including a plurality of transistors, and a conductive line for coupling at least two of the transistors with each other, each transistor comprising a drain diffusion region, a source diffusion region, a gate region, and a test diffusion region within the substrate, the test diffusion region being electrically coupled to a metal line within the semiconductor integrated circuit for establishing an indication of the voltage at the probing diffusion region.

Abstract translation: 半导体集成电路包括包括多个晶体管的基板和用于将至少两个晶体管彼此耦合的导线，每个晶体管包括漏扩散区，源极扩散区，栅极区和测试扩散 区域，所述测试扩散区域电耦合到所述半导体集成电路内的金属线路，用于建立所述探测扩散区域处的电压的指示。

公开(公告)号：US6081466A

公开(公告)日：2000-06-27

申请号：US183451

申请日：1998-10-30

Applicant: David C. McClure ,  Tom Youssef

Inventor： David C. McClure ,  Tom Youssef

IPC: G11C29/08 ,  G11C29/34 ,  G11C00/07

CPC classification number: G11C29/08 ,  G11C29/34

Abstract: A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

Abstract translation: 低/零功率存储器件包括取消选择操作模式，其中禁用字线和列激活所需的存储器件的行解码器，列解码器，写解码器，预编码器，后编码器等操作电路，直到等待 存储器件电源电压超过一定阈值。 附带的测试模式电路检测测试模式激活，并覆盖设备的电源故障解除操作模式的应用。 这在上电时立即激活字线和列相关的操作电路，使得器件通过激活的多个字线和列上电，并准备应用压力测试过电压。

公开(公告)号：US6072732A

公开(公告)日：2000-06-06

申请号：US183444

申请日：1998-10-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C7/22

Abstract: A memory, such as a static random access memory (SRAM), includes at least one memory cell. The bit lines for that memory cell are selectively connected to corresponding write bit lines through a column select pass transistor and a selectively blowable fuse. A reset circuit is connected to the same write bit lines through a fuse structure mimic circuit. Responsive to data transitions on the write bit lines, the reset circuit operates to detect the occurrence of a memory operation to the memory cell and generate a reset signal for resetting the memory in preparation for a next write operation. To support substantially simultaneous presentation of write data to both the reset circuit and the memory cell, the fuse structure mimic circuit delays presentation of the write bit line data to the reset circuit. This introduced delay substantially corresponds to a delay in the presentation of the write bit line data to the memory cell resulting from driving the memory cell bit lines through the selectively blowable fuses.

Abstract translation: 诸如静态随机存取存储器（SRAM）的存储器包括至少一个存储器单元。 该存储单元的位线通过列选择通过晶体管和选择性可熔断保险丝选择性地连接到相应的写位线。 复位电路通过熔丝结构模拟电路连接到相同的写位线。 响应于写入位线上的数据转换，复位电路用于检测对存储器单元的存储器操作的发生，并产生用于复位存储器的复位信号以准备下一次写入操作。 为了基本上同时向复位电路和存储单元提供写入数据，熔丝结构模拟电路将写入位线数据的显示延迟到复位电路。 这种引入的延迟基本上对应于通过可选择性地可熔化的熔丝驱动存储单元位线而将写入位线数据呈现给存储器单元的延迟。

公开(公告)号：US6058778A

公开(公告)日：2000-05-09

申请号：US957809

申请日：1997-10-24

Applicant: Tsiu Chiu Chan ,  Melvin Joseph DeSilva

Inventor： Tsiu Chiu Chan ,  Melvin Joseph DeSilva

IPC: B81B3/00 ,  B81B7/02 ,  G01P15/08 ,  G01P15/135 ,  G01P15/18

CPC classification number: G01P15/18 ,  B81C1/00246 ,  G01P15/0802 ,  G01P15/135 ,  B81B2201/014 ,  B81C2203/0735

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths. The methods of forming an integrated sensor advantageously are preferably compatible with know integrated circuit manufacturing processes, such as for CMOS circuit manufacturing, with only slight variations therefrom.

Abstract translation: 提供集成电路和方法用于感测诸如预定运动方向的加速度的活动。 集成释放的光束传感器优选地包括开关检测电路区域和连接到并且位于开关检测电路区域附近的传感器开关区域。 传感器切换区域优选地包括多个浮动触点，其位于邻近并纵向地从所述开关检测电路区域向外延伸，用于限定多个释放的波束，使得所述多个释放波束中的每一个响应加速度以预定方向移动。 多个释放的光束优选地包括至少两个从开关检测电路区域向外延伸到不同预定长度的释放光束，以及至少两个从开关检测电路区域向外延伸到大致相同的预定长度的释放光束。 有利地形成集成传感器的方法优选地与知道的集成电路制造工艺相兼容，例如用于CMOS电路制造，仅具有轻微的变化。