Abstract:
A method and circuit are disclosed for enabling an oscillator circuit to oscillate a predetermined period of time following completion of a power-up operation. The circuit may include a counter having a control for receiving a control signal from a system power-on-reset circuit, and a clock input. A ring oscillator has an output coupled to the clock input of the counter.
Abstract:
A temperature compensated clock and method of clocking systems are provided. The clock preferably has an oscillator for generating an oscillating waveform signal at a preselected frequency and a frequency divider responsive to the oscillator for dividing the frequency of the oscillating waveform signal. A temperature monitoring circuit is positioned responsive to a voltage input signal independent of temperature and a voltage input signal proportional to temperature for monitoring temperature variations. A temperature compensating circuit, preferably including a programmable scaling circuit, is responsive to the frequency divider and the temperature monitoring circuit for scaling the divided frequency of the generated waveform and thereby advantageously produces a temperature compensated output timing signal.
Abstract:
A frequency test circuit (200) includes a built-in self test (BIST) circuit (212) which provides for testing of a frequency generating circuit such as an oscillator circuit (100). The test circuit (200) includes circuit stages (202-208) which help produce a reference signal (210) which has substantially the same frequency as that produced by the oscillator circuit (100) when it is operational. Since the low current oscillator circuit (100) can fail at any one of the divider or level shifting stages (106-112), the test circuit (200) can determine if the reference signal and the output signal of the oscillator have substantially the same frequency and produce a test condition signal indicative of either a pass or failed test at test port (214).
Abstract:
A method and circuit are disclosed for detecting the performance of an oscillator circuit. In particular, the circuit may detect a signal, such as the output of the oscillator circuit, failing to oscillate as desired. The second circuit may be capable of detecting whether the signal oscillates at a frequency that is less than a predetermined frequency. The second circuit may include timing circuits for determining whether the signal remains in a first logic state for at least a predetermined period of time and whether the signal remains in a second logic state for at least the predetermined period of time.
Abstract:
A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.
Abstract:
A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage. Pass gates control which end of the resistive load series is connected to the output of the voltage follower and which is connected to the output of the trim circuit. To decrement the reference voltage, a first end is connected to the output of the voltage follower and the second end is connected to trim circuit output; to increment the reference voltage, the second end of the resistive load series is connected to the voltage follower output and the first end is connected to the trim circuit output.
Abstract:
An apparatus and method for switching between two power supplies, a primary power supply and a secondary power supply. The present invention generates a first reference voltage using the voltage of the primary power supply and the secondary power supply, wherein the primary power supply voltage is variable. The present invention also generates a second reference voltage based on the voltage of the primary power supply. The first and second reference voltages each have a different slope and the crossing point between these two reference voltages indicate that a switch between the primary power supply and the secondary power supply should occur.
Abstract:
An integrated circuit and method are provided for generating current for low power applications. The integrated circuit preferably includes a current generating circuit responsive to a supply voltage for generating a first reference current and a temperature compensating voltage controlling circuit for generating a temperature compensated voltage control signal during temperature variations. A bias controlling circuit is preferably connected to the current generating circuit and the temperature compensating voltage control circuit for biasingly controlling the temperature compensating voltage control circuit. A current output controlling circuit is connected to the current generating circuit and the temperature compensating voltage controlling circuit for controlling a second temperature compensated reference current responsive to the temperature compensated voltage control signal so as to generate a high output source current even during low temperature conditions.
Abstract:
A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.
Abstract:
A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.