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    Protection of a rijndael algorithm
    511.
    发明授权
    Protection of a rijndael algorithm 有权

    公开(公告)号：US10187198B2

    公开(公告)日：2019-01-22

    申请号：US15046114

    申请日：2016-02-17

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Nicolas Bruneau

    IPC: H04L9/00 ,  G09C1/00 ,  H04L9/06

    Abstract: A method of protecting a Rijndael-type algorithm executed by an electronic circuit against side channel attacks, wherein: each block of data to be encrypted or decrypted is masked with a first mask before applying a non-linear block substitution operation from a first substitution box, and is then unmasked by a second mask after the substitution; the substitution box is recalculated, block by block, before applying the non-linear operation, the processing order of the blocks of the substitution box being submitted to a random permutation; and the recalculation of the substitution box uses the second mask as well as third and fourth masks, the sum of the third and fourth masks being equal to the first mask.

    Configurable delay line
    513.
    发明授权
    Configurable delay line 有权

    公开(公告)号：US10187040B2

    公开(公告)日：2019-01-22

    申请号：US15700475

    申请日：2017-09-11

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Albert Martinez

    IPC: H03H11/26 ,  H03L7/06

    Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.

    Method for reading an EEPROM and corresponding device
    514.
    发明授权
    Method for reading an EEPROM and corresponding device 有权

    公开(公告)号：US10186320B2

    公开(公告)日：2019-01-22

    申请号：US15659891

    申请日：2017-07-26

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

    IPC: G11C7/00 ,  G11C16/26 ,  G11C7/06 ,  G11C16/04 ,  G11C16/24

    Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

    Method of communication over a two-wire bus
    518.
    发明授权
    Method of communication over a two-wire bus 有权

    公开(公告)号：US10135625B2

    公开(公告)日：2018-11-20

    申请号：US14984073

    申请日：2015-12-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Yvon Bahout

    IPC: H02J1/00 ,  H04L12/10 ,  G06F13/42

    Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.

    DIGITAL-TO-ANALOG CONVERTER
    520.
    发明申请
    DIGITAL-TO-ANALOG CONVERTER 审中-公开

    公开(公告)号：US20180323793A1

    公开(公告)日：2018-11-08

    申请号：US15946324

    申请日：2018-04-05

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Vincent ONDE ,  Jean-Francois LINK

    IPC: H03M1/06

    Abstract: A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.

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