公开(公告)号：US20210111214A1

公开(公告)日：2021-04-15

申请号：US17128604

申请日：2020-12-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY ,  Sonarith CHHUN

IPC: H01L27/146

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US10978487B2

公开(公告)日：2021-04-13

申请号：US16288737

申请日：2019-02-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Hassan El Dirani ,  Pascal Fonteneau

IPC: H01L29/76 ,  H01L27/12 ,  H02M7/5387 ,  H01L29/417 ,  H03K19/10 ,  H03K19/00 ,  H03K19/094

Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

公开(公告)号：US10978340B2

公开(公告)日：2021-04-13

申请号：US16384147

申请日：2019-04-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L27/12 ,  H01L27/146 ,  H01L27/06 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/74 ,  H01L21/02

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US10971533B2

公开(公告)日：2021-04-06

申请号：US15882482

申请日：2018-01-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146 ,  H04N5/374 ,  H04N5/378 ,  H04N5/357

Abstract: In an embodiment, an image sensor includes a semiconductor region, a first doped region disposed over the semiconductor region, a ring shaped well disposed over the first doped region and surrounding parts of the first doped region, a second doped region formed within the ring shaped well and disposed over the first doped region, and a third doped region disposed over the second doped region. The ring shaped well is defined by a conductor surrounded by an insulator. The conductor is connected to a voltage terminal. The third doped region is more heavily doped than the second doped region, which is more heavily doped than the first region, and are all of the same doping type. The first doped region and the second doped region within the ring shaped well, form a potential barrier for controlling transfer of charge carriers from the first doped region to the third doped region.

公开(公告)号：US10951844B2

公开(公告)日：2021-03-16

申请号：US15953925

申请日：2018-04-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: G01C3/08 ,  H04N5/369 ,  H04N5/378 ,  H04N5/353 ,  H01L27/146 ,  G01S7/4863

Abstract: A time-of-flight detection pixel includes a photosensitive area and at least two assemblies. Each assembly includes: a charge storage area; a transfer transistor configured to control charge transfer from the photosensitive area to the charge storage area; and readout circuit configured to non-destructively measure a quantity of charges stored in the charge storage area.

公开(公告)号：US20210057521A1

公开(公告)日：2021-02-25

申请号：US16995079

申请日：2020-08-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER ,  Gregory AVENIER

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8222 ,  H01L29/732

Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.

公开(公告)号：US20210057329A1

公开(公告)日：2021-02-25

申请号：US16546569

申请日：2019-08-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522 ,  H01L27/11524 ,  H01L49/02

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20210033894A1

公开(公告)日：2021-02-04

申请号：US17064385

申请日：2020-10-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Patrick Le Maitre ,  Nicolas Michit ,  Jean-Francois Carpentier ,  Benoit Charbonnier

IPC: G02F1/025 ,  G01R19/30

Abstract: A device, includes: a ring waveguide; a diode comprising a junction extending at least partly in the ring waveguide; and a first circuit configured to supply a signal representative of a leakage current in the diode.

公开(公告)号：US10903423B2

公开(公告)日：2021-01-26

申请号：US16708604

申请日：2019-12-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Pierre Morin ,  Michel Haond ,  Paola Zuliani

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

公开(公告)号：US20210018790A1

公开(公告)日：2021-01-21

申请号：US16931202

申请日：2020-07-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Cremer

IPC: G02F1/1333 ,  G02F1/01 ,  G02B6/13

Abstract: A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.