公开(公告)号：US5874338A

公开(公告)日：1999-02-23

申请号：US493149

申请日：1995-06-21

Applicant: Giuseppe Ferla ,  Ferruccio Frisina

Inventor： Giuseppe Ferla ,  Ferruccio Frisina

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/66712 ,  H01L29/1095

Abstract: A MOS-technology power device including a semiconductor material layer of a first conductivity type having a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type and a process of making same. A method of making the semiconductor device includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. Ions of the second conductivity type are implanted into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. Ions of the first conductivity type are then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.

Abstract translation: 一种MOS技术的功率器件，包括具有设置在其中的体区的第一导电类型的半导体材料层。 体区包括第二导电类型的重掺杂区域，第二导电类型的轻掺杂区域和第一导电类型的重掺杂区域及其制造方法。 制造半导体器件的方法包括在半导体材料层的表面的部分上形成绝缘栅极层，以使半导体材料层的选定部分露出。 第二导电类型的离子注入到半导体材料层的选定区域中。 注入的离子热扩散以形成体区，每个体区包括基本上与绝缘栅层的边缘对准的重掺杂区，以及通过第一掺杂剂在绝缘栅层下方的横向扩散形成的轻掺杂区。 然后将第一导电类型的离子注入到重掺杂区域中以形成与绝缘栅极层的边缘基本对准的源极区域。

公开(公告)号：US5859810A

公开(公告)日：1999-01-12

申请号：US826009

申请日：1997-03-27

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C7/10 ,  G11C7/22 ,  G11C13/00

CPC classification number: G11C7/106 ,  G11C7/1051 ,  G11C7/22

Abstract: A memory device that includes an internal bus for the transfer of data and reporting signals from and to the memory and output pre-buffers for the transfer of data to output terminals of said memory, a pulse generation circuit for the synchronized loading of data in an output pre-buffer. Additional circuitry is provided that includes a synchronization circuit; a transmission path delay reproduction circuit for reproducing the propagation delays of the data transmitted to the output terminals; and a pre-buffer delay reproduction circuit for reproducing the propagation delays of the output pre-buffers. The synchronization circuit is adapted to synchronize the generation of at least one pulse that is synchronized with the propagation delays reproduced by the transmission path delay reproduction circuit, and the pulse is adapted to enable the loading of the data in the output pre-buffers. The synchronization of the pulse is provided as a consequence of the assured presence of the data, and the synchronous pulse is restored after a time that is equal to the delay introduced by the pre-buffer delay reproduction circuit for reproducing the propagation delays of the output pre-buffers, so as to update the configuration of the output pre-buffers in the time interval determined by the synchronous pulse.

Abstract translation: 一种存储器件，其包括用于从存储器传送数据和向存储器报告信号的内部总线，并输出用于将数据传送到所述存储器的输出端的预缓冲器，脉冲发生电路，用于在 输出预缓冲区。 提供了包括同步电路的附加电路; 传输路径延迟再现电路，用于再现传输到输出端的数据的传播延迟; 以及用于再现输出预缓冲器的传播延迟的预缓冲器延迟再现电路。 同步电路适于同步与由传输路径延迟再现电路再现的传播延迟同步的至少一个脉冲的产生，并且该脉冲适于使能将数据加载在输出预缓冲器中。 作为数据的确定存在的结果，提供了脉冲的同步，并且在等于由预缓冲器延迟再生电路引入的用于再现输出的传播延迟的延迟的时间之后恢复同步脉冲 预缓冲器，以便在由同步脉冲确定的时间间隔内更新输出预缓冲器的配置。

公开(公告)号：US5854770A

公开(公告)日：1998-12-29

申请号：US791746

申请日：1997-01-30

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12

CPC classification number: G11C8/12 ,  G11C8/00 ,  G11C8/10

Abstract: A nonvolatile static memory includes a matrix of elementary cells addressable through bit-lines (columns) and word-lines (rows) mutually orthogonal among each other, the matrix being divided in two orders of subblocks, respectively left and right, aligned in a direction of extension of the word-lines and symmetrical by pairs. At least one row predecoding circuit and a plurality of row decoding circuits are provided for the subblocks. Column predecoding circuits and a plurality of column multiplexers are provided for the subblocks and controlled by the column predecoding circuits. A first main predecoding circuit of the address bus generates a first bus, a second bus and a third bus. In addition, a pair of main row decoding circuits combines signals of the first, second and third buses and generates a resulting number of main row decoding lines, each stimulating respective row decoding circuits of the right and left subblocks. Two pairs of local row predecoding circuits are provided for each of the right and left subblocks, a first pair for word-lines of even order and a second pair for word-lines of odd order of the right and left subblocks, respectively, and are stimulated by the address bus to generate a fourth bus and a fifth bus, respectively.

Abstract translation: 非易失性静态存储器包括通过位线（列）和彼此相互正交的字线（行）可寻址的基本单元矩阵，矩阵分成左右两个子块，分别左右排列 的字线延伸和对对称。 为子块提供至少一行预解码电路和多个行解码电路。 为子块提供列预解码电路和多个列复用器，并由列预解码电路控制。 地址总线的第一主要预解码电路产生第一总线，第二总线和第三总线。 此外，一对主行解码电路组合第一，第二和第三总线的信号，并且产生最终数量的主行解码行，每一行激励左和右子块的各个行解码电路。 为左右子块分别设置两对本地行预解码电路，第一对是偶数字的字线，第二对为左右子块的奇数行的字线，分别为 由地址总线分别产生第四总线和第五总线。

公开(公告)号：US5854764A

公开(公告)日：1998-12-29

申请号：US821804

申请日：1997-03-21

Applicant: Corrado Villa ,  Marco Dallabora ,  Fabio Tassan Caser

Inventor： Corrado Villa ,  Marco Dallabora ,  Fabio Tassan Caser

IPC: G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C15/00 ,  G11C13/00

CPC classification number: G11C29/82

Abstract: A sectorized electrically erasable and programmable non-volatile memory device comprises: a plurality of individually-addressable memory sectors, each memory sector comprising an array of memory cells arranged in rows and columns; redundancy columns of redundancy memory cells for replacing defective columns of memory cells; and a redundancy control circuit for storing addresses of the defective columns and activating respective redundancy columns when said defective columns are addressed. Each memory sector comprises at least one respective redundancy column. The redundancy control circuit comprises at least one memory means comprising individually addressable memory locations each one associated with a respective memory sector for storing, individually for each memory sector, addresses of a defective column belonging to the memory sector, and an address recognition means associated with said memory means for recognizing if a current address supplied to the memory device coincides with a defective column address stored in an addressed one of said memory locations associated with a currently addressed memory sector.

Abstract translation: 扇区化的电可擦除和可编程的非易失性存储器设备包括：多个可单独寻址的存储器扇区，每个存储器扇区包括以行和列布置的存储器单元的阵列; 用于替换存储器单元的有缺陷的列的冗余存储单元的冗余列; 以及冗余控制电路，用于存储所述缺陷列的地址，并且当所述缺陷列被寻址时激活相应的冗余列。 每个存储器扇区包括至少一个相应的冗余列。 冗余控制电路包括至少一个存储器装置，其包括单独可寻址的存储器位置，每个存储器位置与相应的存储器扇区相关联，每个存储器单元分别存储针对每个存储器扇区的属于存储器扇区的缺陷列的地址，以及与 所述存储器装置用于识别提供给存储器件的当前地址是否与存储在与当前寻址的存储器扇区相关联的所述存储器位置中的所寻址的一个存储器中的有缺陷的列地址一致。

公开(公告)号：US5841728A

公开(公告)日：1998-11-24

申请号：US724495

申请日：1996-09-30

Applicant: Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

Inventor： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC: G11C8/12 ,  G11C8/14 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C8/14

Abstract: The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.

Abstract translation: 根据本发明的存储器件具有分级行解码架构，并且包括至少一个主解码器和多个辅助解码器。 解码器具有通过分别连接到分别连接到字线的中间点的所述输出和第二端的多个辅助线耦合到多个字线的输出。

公开(公告)号：US5838619A

公开(公告)日：1998-11-17

申请号：US828039

申请日：1997-03-27

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C29/00 ,  G06F11/20

CPC classification number: G11C29/84

Abstract: A redundancy management method, particularly for non-volatile memories, includes the steps of: enabling, as a consequence of the presence of a pulsed read address transition signal of a memory line, and throughout the duration of the pulsed signal, the memory matrix line reading path, and blocking the selection of redundancy lines of the memory; and at the end of the pulsed signal, as a consequence of the absence/presence of a redundancy line read signal, confirming/disabling the selection of the lines of the memory matrix and blocking/releasing the selection of the redundancy lines. A redundancy management architecture for a memory matrix, adapted to perform the above method, blocks or releases redundancy line selection during address switching, but does not block selection of memory matrix word lines.

Abstract translation: 特别是用于非易失性存储器的冗余管理方法包括以下步骤：由于存在存储线的脉冲读地址转换信号的存在，并且在脉冲信号的整个持续时间内，存储矩阵线 读取路径，阻止存储器冗余线的选择; 并且在脉冲信号结束时，由于不存在/存在冗余线路读取信号，确认/禁止对存储器矩阵的行的选择并阻止/释放冗余线的选择。 用于执行上述方法的存储矩阵的冗余管理架构在地址切换期间阻止或释放冗余线选择，但不阻止对存储矩阵字线的选择。

公开(公告)号：US5838612A

公开(公告)日：1998-11-17

申请号：US869072

申请日：1997-06-04

Applicant: Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC: G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C11/34

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

Abstract: Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

Abstract translation: 用于多电平非易失性存储单元器件的读取电路，对于要读取的每个单元，具有与负载和去耦合和控制级相关联的选择线，其具有稳定选择线的电路节点上的电压的反馈环路 。 对该节点连接由反馈回路控制的当前复制电路。 这些包括与与存储器单元的选择线相关的负载和电路元件同源的负载和电路元件，并且具有用于连接到电流比较器电路的输出接口电路。

公开(公告)号：US5822259A

公开(公告)日：1998-10-13

申请号：US846755

申请日：1997-04-30

Applicant: Marco Maccarrone ,  Stefano Ghezzi ,  Maurizio Branchetti

Inventor： Marco Maccarrone ,  Stefano Ghezzi ,  Maurizio Branchetti

IPC: G11C16/04 ,  G11C16/24 ,  G11C7/00

CPC classification number: G11C16/24 ,  G11C16/0433

Abstract: The present invention is directed to a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type having a control terminal and a conduction terminal to be biased, a register with inverters connected to the memory element, and MOS transistors connecting the memory element with a reference low voltage power supply. There is provided a precharge network for the conduction terminal of the flash cell and the network incorporates a complementary pair of transistors. The second transistor of the pair is a natural N-channel MOS type. With the UPROM cell is associated a circuit portion for generating a second live output signal to be applied to the control terminal of the second transistor. The circuit portion includes a timing section and a generation section for the second live output signal.

Abstract translation: 本发明涉及一种包含至少一个EPROM或闪存类型的存储元件的冗余UPROM单元，其具有控制端子和要偏置的导通端子，具有连接到存储元件的反相器的寄存器和连接存储器的MOS晶体管 元件与参考低压电源。 提供了用于闪存单元的导通端子的预充电网络，并且网络包含互补的一对晶体管。 该对的第二晶体管是自然的N沟道MOS型。 与UPROM单元相关联的电路部分用于产生要施加到第二晶体管的控制端的第二实时输出信号。 电路部分包括定时部分和用于第二实时输出信号的生成部分。

公开(公告)号：US5821788A

公开(公告)日：1998-10-13

申请号：US790832

申请日：1997-01-30

Applicant: Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

Inventor： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC: G11C5/14 ,  H03L7/00

CPC classification number: G11C5/143

Abstract: A power-on-reset (P.O.R.) circuit produces a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on a supply node until it exceeds a certain threshold. The circuit has a first monitoring and comparing circuit portion including at least a nonvolatile memory element having a control gate coupled to the supply node, a first current terminal coupled to a ground node, and a second current terminal coupled to a first node which is capacitively coupled to the supply node. The circuit further includes a second circuit portion that includes an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to the first node that is intrinsically in a low state at power-on coupled to the input of an output buffer.

Abstract translation: 上电复位（P.O.R.）电路产生上电复位（P.O.R.）信号，其幅度跟踪供电节点上的电压，直到其超过某个阈值。 该电路具有第一监视和比较电路部分，该电路部分至少包括具有耦合到电源节点的控制栅极的非易失性存储器元件，耦合到接地节点的第一电流端子和耦合到电容性的第一节点的第二电流端子 耦合到供应节点。 该电路还包括第二电路部分，该第二电路部分包括本质上不平衡的双稳态电路，其具有在上电时本质上处于处于高状态的节点，所述节点在与所述输入端相连的上电时本质上处于处于低电平状态 的输出缓冲区。

公开(公告)号：US5812467A

公开(公告)日：1998-09-22

申请号：US841903

申请日：1997-04-17

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C29/00 ,  G11C13/00

CPC classification number: G11C29/789 ,  G11C29/80

Abstract: A redundancy memory register for storing defective addresses of defective memory elements in a memory device includes a plurality of memory units each one storing a respective defective address bit and comparing the defective address bit stored therein with a respective current address bit of a current address supplied to the memory device. The register includes a first group of memory units and a second group of memory units storing a first defective address, and a third group of memory units storing, together with the first group, a second defective address which has an address part in common with the first defective address. The first and second group of memory units supply first redundancy selection means for selecting a first redundancy memory element when the current address coincides with the first defective address. The first and third group of memory units supply second redundancy selection means for selecting a second redundancy memory element when the current address coincides with the second defective address. The register comprises first address configuration detection means for detecting if the current address coincides with a default configuration stored in the first and second group of memory units and for correspondingly deactivating the first and second redundancy selection means, and second address configuration detection means for detecting if the current address coincides with a default configuration stored in the third group of memory units and for consequently deactivating the second redundancy selection means.

Abstract translation: 用于将有缺陷的存储器元件的缺陷地址存储在存储器件中的冗余存储器寄存器包括多个存储单元，每个存储器单元存储相应的缺陷地址位，并将存储在其中的缺陷地址位与当前地址的相应当前地址位进行比较， 存储设备。 寄存器包括第一组存储器单元和存储第一缺陷地址的第二组存储单元，以及第三组存储单元，与第一组一起存储第二缺陷地址，该第二缺陷地址具有与 第一个缺陷地址。 第一和第二组存储器单元提供第一冗余选择装置，用于当当前地址与第一缺陷地址一致时，选择第一冗余存储元件。 第一和第三组存储器单元提供第二冗余选择装置，用于当当前地址与第二缺陷地址一致时选择第二冗余存储元件。 寄存器包括第一地址配置检测装置，用于检测当前地址是否与存储在第一和第二组存储器单元中的默认配置一致，并且相应地去激活第一和第二冗余选择装置;以及第二地址配置检测装置，用于检测是否 当前地址与存储在第三组存储器单元中的默认配置一致，并且因此停用第二冗余选择装置。