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    MICRO-ELECTRO-MECHANICAL SYSTEM STRUCTURE AND METHOD FOR FABRICATING THE SAME
    551.
    发明申请
    MICRO-ELECTRO-MECHANICAL SYSTEM STRUCTURE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20200223687A1

    公开(公告)日：2020-07-16

    申请号：US16284735

    申请日：2019-02-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yuan-Sheng LIN ,  Jung-Hao CHANG ,  Chang-Sheng HSU ,  Weng-Yi CHEN

    IPC: B81B7/00 ,  B81C1/00

    Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.

    High electron mobility transistor
    552.
    发明授权
    High electron mobility transistor 有权

    公开(公告)号：US10714607B1

    公开(公告)日：2020-07-14

    申请号：US16294893

    申请日：2019-03-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Kuan-Hung Liu

    IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/207

    Abstract: According to an embodiment of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a carrier transit layer on the buffer layer; a carrier supply layer on the carrier transit layer; a gate electrode on the carrier supply layer; and a source and a drain adjacent to two sides of the gate electrode. Preferably, the carrier supply layer comprises a concentration gradient of aluminum (Al).

    Semiconductor memory device and fabrication method thereof
    553.
    发明授权
    Semiconductor memory device and fabrication method thereof 有权

    公开(公告)号：US10707225B2

    公开(公告)日：2020-07-07

    申请号：US16792847

    申请日：2020-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28

    Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    556.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200211899A1

    公开(公告)日：2020-07-02

    申请号：US16811830

    申请日：2020-03-06

    Applicant: United Microelectronics Corp.

    Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

    IPC: H01L21/8249 ,  H01L21/768 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

    Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.

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