公开(公告)号：US20240281373A1

公开(公告)日：2024-08-22

申请号：US18441945

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F12/02 ,  G06F12/123

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/123

Abstract: Methods, systems, and devices for a memory system host data reset function are described. A reset operation may be performed to reset data in a memory system without erasing host data from the memory system. The memory system and a host system may perform the reset operation to sequentially reorder the data across pages and blocks of the memory system, mitigating holes in the data. The reset operation may enable sequentially reordering the data by performing refresh operations on the blocks and performing a subsequent garbage collection operation to consolidate the data within the pages of the refreshed blocks. The host system may reorganize the logical block addresses associated with the blocks and the memory system may perform the refresh operations and the garbage collection operations. The blocks may be refreshed according to an order of access frequency and according to a measure of performance impact on the memory system.

公开(公告)号：US20240281371A1

公开(公告)日：2024-08-22

申请号：US18586144

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Giuseppe Cariello

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/126 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0679 ,  G06F12/126 ,  G06F13/1668 ,  G06F2212/7201 ,  G06F2212/7207

Abstract: Methods, systems, and devices for usage level identification for memory device addresses are described. Systems, techniques, and devices are described herein in which a memory device may determine where to store data according to a level of usage of the data. The memory device may receive a write command indicating data to be written, a type of the data, and a logical address of a memory array for writing the data. The memory device may identify an entry associated with the logical address in a table that maps the logical address to a physical address of the memory array. The entry may include a field configured to maintain a level of usage for the logical address. The memory device may update the level of usage value according to a process and write the data to a physical address of the memory array based on the level of usage value.

公开(公告)号：US20240281350A1

公开(公告)日：2024-08-22

申请号：US18581189

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F11/263

CPC classification number: G06F11/263

Abstract: Methods, systems, and devices for improved testing for memory devices using dedicated command and address (CA) channels are described. A memory system associated with the memory devices may include a buffer configured to store a channel select indicator that indicates which CA channel to be utilized for various access commands associated with the memory devices. The memory system may utilize headers to facilitate the data transfers between the associated memory devices and testing system via the indicated CA channel using the buffer. The memory system may detect a select chip enable command on the CA channel and may subsequently store the channel select indicator in the buffer. The memory system may then detect data on the dedicated CA channel and subsequently read the stored channel select indicator from the buffer. The memory system may then erase the channel select indicator from the buffer, after receiving a select chip terminate command.

公开(公告)号：US20240281324A1

公开(公告)日：2024-08-22

申请号：US18443011

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Caixia Yang

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1064 ,  G06F11/076 ,  G06F11/1016

Abstract: Methods, systems, and devices for critical data management within a memory system are described. A memory system may avoid writing critical data to weak word lines. For example, as part of a media management operation or a host write operation (among other examples), the memory system may determine which data is critical data and may determine which word lines are weak word lines, which may refer to word lines having bit error rates that satisfy a threshold. The memory system may refrain from writing critical data to memory cells coupled with weak word lines, and may instead write non-critical or dummy data to the weak word lines. The memory system may reserve the writing of critical data to memory cells coupled with non-weak word lines, which may refer to word lines having bit error rates that fail to satisfy the threshold.

公开(公告)号：US20240281322A1

公开(公告)日：2024-08-22

申请号：US18440067

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: A system for providing a voting scheme in a memory page is disclosed. The system receives a request from a host device for data. The system identifies a memory page of a memory array of a memory device storing data bits corresponding to the requested data. The data bits are transferred from memory cells of the memory page to sense amplifiers to sense the values of the data bits. Inversion bits for the row address(es) of the memory page are transferred to a voting circuit to conduct a vote using the inversion bits. If the vote indicates that the data bits are inverted, the system flips the data bits prior to providing the data bits to the host device. If the vote indicates that the data bits are not inverted, the system provide the data bits to the host device without flipping the data bits.

公开(公告)号：US20240281289A1

公开(公告)日：2024-08-22

申请号：US18436881

申请日：2024-02-08

Applicant: Micron Technology, Inc.

Inventor： Pavana Prakash ,  Shashank Bangalore Lakshman ,  Febin Sunny ,  Saideep Tiku ,  Poorna Kale

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: Decomposing an operation can include dividing the operation into a plurality of portions of the operation. A different portion can be provided from the plurality of portions to each group from the plurality of groups of edge devices. The input values can be provided to each of the plurality of groups of edge devices. A plurality of outputs can be received from the plurality of groups of edge devices generated using the input values and the plurality of portions. The plurality of outputs can be recomposed into a single output for the operation.

公开(公告)号：US20240281275A1

公开(公告)日：2024-08-22

申请号：US18433181

申请日：2024-02-05

Applicant: Micron Technology, Inc.

Inventor： Satheesh Babu MUTHUPANDI

IPC: G06F9/455 ,  G06F13/40

CPC classification number: G06F9/45558 ,  G06F13/4022 ,  G06F13/409 ,  G06F2009/45583

Abstract: A system comprises a chassis; a Compute Express Link (CXL) back plane interface mounted within the chassis; a first printed circuit board housed within the chassis and connected to the CXL back plane interface, the first printed circuit board including processing circuitry, switching circuitry and a memory; and a blade server comprising a second printed circuit board housed within the chassis and connected to the CXL back plane interface. The processing circuitry is configured to control the switching circuitry to allocate at least a portion of the memory to the blade server such that a virtual machine provided by the blade server can access the allocated memory through the CXL back plane interface in addition to its own dedicated memory provided by the blade server.

公开(公告)号：US20240281162A1

公开(公告)日：2024-08-22

申请号：US18434375

申请日：2024-02-06

Applicant: Micron Technology, Inc.

Inventor： Amiya Banerjee ,  Thibash Rajamani Balakrishnan

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0652 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods, systems, and devices for synchronizing operations between decks of a memory system are described. In some examples, a memory system may determine a PEC difference between sister decks of physical blocks of the memory system. A memory system controller may associate the sister decks with respective virtual blocks. The controller may scan each virtual block of the memory system to determine which blocks are to be recycled, and may generate a list of virtual blocks having a VPC that satisfies a first threshold. In some cases, the controller may perform one or more threshold comparisons to determine whether to perform the maintenance operation on the first sister deck or both the first sister deck and the second sister deck.

公开(公告)号：US20240281145A1

公开(公告)日：2024-08-22

申请号：US18439318

申请日：2024-02-12

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung LIEN ,  Zhenming ZHOU

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and apparatuses include determining an erase policy for a memory device. An erase operation is selected based on the determined erase policy, where the erase operations include an alternating erase operation and a uniform erase operation. The erase operation is executed on a portion of memory.

公开(公告)号：US12069856B2

公开(公告)日：2024-08-20

申请号：US18047214

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H10B41/27 ,  H10B41/10 ,  H10B51/00

CPC classification number: H10B41/27 ,  H10B51/00 ,  H10B41/10

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.