公开(公告)号：US07400195B2

公开(公告)日：2008-07-15

申请号：US11404585

申请日：2006-04-14

Applicant: Paolo Gatti

Inventor： Paolo Gatti

IPC: H03F3/45

CPC classification number: H03F3/45475

Abstract: A variable-gain amplifier with high input impedance includes positive and negative inputs, positive and negative outputs, first and second differential circuits and first, second and third impedances. The impedances form an impedance bridge between the outputs. The first and second differential circuits each have one input coupled to one of the inputs of the differential amplifier, one input coupled to the impedance bridge, and two outputs connected to the outputs of the differential amplifier. At least one of the impedances is a variable impedance.

Abstract translation: 具有高输入阻抗的可变增益放大器包括正和负输入，正负输出，第一和第二差分电路以及第一，第二和第三阻抗。 阻抗在输出之间形成阻抗桥。 第一差分电路和第二差分电路各自具有耦合到差分放大器的一个输入的一个输入，耦合到阻抗桥的一个输入和连接到差分放大器的输出的两个输出。 阻抗中的至少一个是可变阻抗。

公开(公告)号：US20080159014A1

公开(公告)日：2008-07-03

申请号：US11617336

申请日：2006-12-28

Applicant: Cyrille Dray ,  Francois Jacquet

Inventor： Cyrille Dray ,  Francois Jacquet

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: The invention relates to a device, and also to a corresponding method of implementation, for SRAM memory information storage, powered by a voltage VDD and comprising: an array of base cells organised in base columns, and at least one mirror column of mirror cells, liable to simulate the behaviour of the cells in a base column, The invention is characterised in that the device further comprises: Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying the mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 本发明涉及一种由电压VDD供电的SRAM存储器信息存储器的器件以及相应的实现方法，包括：组合在基本列中的基本单元阵列，以及镜像单元的至少一个反射镜列， 本发明的特征在于，该装置还包括：在反射镜列中的仿真装置，其是基极柱中最大限制电池的装置，用于改变反射镜电源电压的装置 （VDDMMOCK），以及用于复制仿真基列中的反射镜电源电压的装置。

公开(公告)号：US07393215B2

公开(公告)日：2008-07-01

申请号：US11533316

申请日：2006-09-19

Applicant: Eric Saugier

Inventor： Eric Saugier

IPC: H01R12/00

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An assembly structure of a mobile objective above an optical sensor assembled on a support board includes a cover assembled on the support board with an opening facing the sensor, this cover having a conical external surface with an axis orthogonal to the support board. The structure also includes a frame having first and second elements, shiftable with respect to each other under the action of an electric motor. The first frame element has a conical internal surface capable of mating with the conical external surface of the cover to ensure its positioning and to put resilient connection blades of a fixed portion of the motor in contact with pads formed on the support board, and the second frame element supports the objective and a shiftable portion of the motor.

Abstract translation: 组装在支撑板上的光学传感器上方的移动物体的组装结构包括：组装在支撑板上的盖，其具有面向传感器的开口，该盖具有与支撑板正交的轴的圆锥形外表面。 该结构还包括具有第一和第二元件的框架，在电动机的作用下可相对于彼此移动。 第一框架元件具有能够与盖的锥形外表面配合的圆锥形内表面，以确保其定位并且将马达的固定部分的弹性连接叶片与形成在支撑板上的垫接触，并且第二框架元件 框架元件支撑电机的目标和可移动部分。

公开(公告)号：US07386691B2

公开(公告)日：2008-06-10

申请号：US11104836

申请日：2005-04-13

Applicant: Friedbert Berens ,  Michael J. Thul ,  Franck Gilbert ,  Norbert Wehn

Inventor： Friedbert Berens ,  Michael J. Thul ,  Franck Gilbert ,  Norbert Wehn

IPC: G06F12/00 ,  G06F13/00

CPC classification number: H03M13/6566 ,  H03M13/2771

Abstract: An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output data sets respectively associated with the N input data sets stored in the N elementary source memories at respective source addresses. The electronic device may also include N single port target memories, N interleaving tables including, for each relative source address, the number of a target memory and the respective target address thereof, N cells connected in a ring structure. Further, each cell may also be connected between an output of the processor, an interleaving table, and a target memory.

Abstract translation: 电子设备可以包括分为N个基本源存储器的源存储器件，用于存储一系列输入数据组，以及由时钟信号计时并具有N个输出的处理器，用于每个周期的时钟信号产生N个输出数据组 分别与存储在各个源地址中的N个基本源存储器中的N个输入数据集相关联。 电子设备还可以包括N个单端口目标存储器，N个交织表包括用于每个相对源地址的目标存储器的数量及其各自的目标地址，以环形结构连接的N个单元。 此外，每个单元还可以连接在处理器的输出，交织表和目标存储器之间。

公开(公告)号：US07386645B2

公开(公告)日：2008-06-10

申请号：US11120167

申请日：2005-05-02

Applicant: Herve Chalopin ,  Laurent Tabaries

Inventor： Herve Chalopin ,  Laurent Tabaries

IPC: G06F13/36 ,  G06F13/364 ,  G06F12/00 ,  G06F13/18 ,  G06F13/38

CPC classification number: G06F13/362 ,  G06F13/1605

Abstract: An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2≦P≦N and 1≦Q≦N. In the event of a plurality of conflicting requests to access a common resource originating from a plurality of respective initiator modules, an arbitration unit grants an exclusive right of access to the resource to a defined one of these initiator modules. The arbitration unit is constructed either to apply a standard arbitration mechanism to these respective initiators, or to apply as a priority a specific arbitration mechanism only to the members of a subset of these initiator modules, for each of which it receives a linked privileged access signal.

Abstract translation: 一个电子系统包括定义数量的N个功能模块，其中包括定义数量的启动器模块和定义的Q个目标模块，其中N，P和Q是整数，使得2 <= P <= N， = Q <= N。 在多个冲突的请求访问源自多个各自的发起者模块的公共资源的情况下，仲裁单元向所定义的这些发起者模块之一授予访问资源的排他权。 仲裁单元被构造成将标准仲裁机制应用于这些各自的启动器，或者仅将特定仲裁机制作为优先级应用于这些发起者模块的子集的成员，对于每个发起者模块的子集， 。

公开(公告)号：US20080126893A1

公开(公告)日：2008-05-29

申请号：US11772385

申请日：2007-07-02

Applicant: Michel Harrand

Inventor： Michel Harrand

IPC: G11C29/52 ,  G06F11/263

CPC classification number: G11C11/406 ,  G11C7/04 ,  G11C11/40626 ,  G11C2211/4061 ,  G11C2211/4062

Abstract: A method is for refreshing a dynamic random access memory coupled to an error correction system, which uses an error correcting code. The dynamic random access memory includes groups of memory cells storing bits, each group of memory cells being subdivided into packets of memory cells. Each packet of memory cells is supplemented with the error correcting code. The method includes performing a retention test on each group of memory cells, and increasing a memory refresh frequency if a number of test groups of memory cells having at least one erroneous packet is greater than a threshold.

Abstract translation: 一种方法是刷新耦合到使用纠错码的纠错系统的动态随机存取存储器。 动态随机存取存储器包括存储位的存储器单元组，每组存储器单元被细分成存储器单元的分组。 每个存储器单元包被补充有纠错码。 该方法包括对每组存储器单元执行保留测试，并且如果具有至少一个错误分组的存储器单元的测试组的数量大于阈值，则增加存储器刷新频率。

公开(公告)号：US07368986B2

公开(公告)日：2008-05-06

申请号：US11321795

申请日：2005-12-29

Applicant: Gaël Pillonnet

Inventor： Gaël Pillonnet

IPC: H03F3/38

CPC classification number: H03F3/217 ,  H03F1/32 ,  H03F2200/351

Abstract: A digital/analog amplifier includes the following coupled in series: a pulse-width modulator, a control circuit, a power inverter and a filter. The power inverter comprises two transistors series-connected between a power supply terminal and a ground of the amplifier. The control circuit drives the transistors of the power inverter. One output of the filter forms an output of the amplifier to which a load is connected. The amplifier also comprises a capacitive circuit parallel-connected to the output of the power inverter.

Abstract translation: 数字/模拟放大器包括以下串联耦合：脉冲宽度调制器，控制电路，功率逆变器和滤波器。 电力逆变器包括串联连接在电源端子和放大器的接地之间的两个晶体管。 控制电路驱动电力逆变器的晶体管。 滤波器的一个输出形成负载连接到的放大器的输出。 放大器还包括并联到电力逆变器的输出的电容电路。

公开(公告)号：US20080094165A1

公开(公告)日：2008-04-24

申请号：US11907217

申请日：2007-10-10

Applicant: Bastien Orlando ,  Bernard Viala

Inventor： Bastien Orlando ,  Bernard Viala

IPC: H01F27/28 ,  H01F17/04

CPC classification number: H01F17/0033 ,  H01F17/04

Abstract: The coil comprises a plurality of non-joined turns, each turn comprising a rectangular bottom flat section in a bottom plane and a rectangular top flat section in a top plane and two rising sections. The turns fill almost all of the enveloping surface of the coil, a minimum isolating gap separating the adjacent turns. The top and bottom sections corresponding to one and the same turn are aligned with respect to one another and have a larger width than the width of the corresponding rising sections. The turns constitute a plurality of substantially parallel coil branches, rising sections of two adjacent branches arranged between the two adjacent branches being arranged alternately in a single plane.

公开(公告)号：US20080061810A1

公开(公告)日：2008-03-13

申请号：US11844627

申请日：2007-08-24

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G01R31/02 ,  G01R31/28

CPC classification number: G01R31/3187 ,  G01R31/2831 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/31717 ,  G01R31/318511

Abstract: A method for testing an integrated circuit is provided comprising steps of providing at least one first conductive path stretching along an element of the integrated circuit, applying a voltage at a point of the first conductive path, performing a first measurement of the voltage at a point of the first conductive path, and determining whether the integrated circuit is damaged according to the result of the first measurement. Application to the detection of damage due to the sawing or electrical testing of integrated circuits.

Abstract translation: 提供一种用于测试集成电路的方法，包括以下步骤：提供沿着集成电路的元件拉伸的至少一个第一导电路径，在第一导电路径的点处施加电压，在一点处执行电压的第一测量 的第一导电路径，并且根据第一测量的结果确定集成电路是否损坏。 应用于检测集成电路锯切或电气测试造成的损坏。

公开(公告)号：US20080048208A1

公开(公告)日：2008-02-28

申请号：US11828855

申请日：2007-07-26

Applicant: John Brunel ,  Nicolas Froidevaux

Inventor： John Brunel ,  Nicolas Froidevaux

IPC: H01L27/06 ,  H01L21/8249

CPC classification number: H01L27/0262

Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or output terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.

Abstract translation: 集成电路由半导体材料制成，并且包括连接到输出晶体管的输入和/或输出端子，该输出晶体管形成在施加到端子的静电放电的作用下能够自身触发的寄生元件。 集成电路包括形成为在静电放电的作用下与寄生元件同时偏置的保护装置，并且优先于排出放电电流的寄生元件。