公开(公告)号：US07301837B2

公开(公告)日：2007-11-27

申请号：US11291478

申请日：2005-11-30

Applicant: Nicolas Demange

Inventor： Nicolas Demange

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/02

Abstract: A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.

Abstract translation: 非易失性存储器包括提供对存储器单元的访问的字线，将字线对应于输入地址的激活信号应用于字线的转换器，转换器通过降低其电压电平来再现输出上的激活信号，以及编码 电路，其包括具有低于输出的电压电平的开关阈值的晶体管，并被耦合，以便如果该字线是唯一被激活的字线，则产生专用于激活字线的输出地址，使得测试电路产生 如果输入地址与输出地址不同，则出现错误信号。 在这样的结构中，可以减少由测试电路占用的硅的面积。

公开(公告)号：US20070257701A1

公开(公告)日：2007-11-08

申请号：US11675265

申请日：2007-02-15

Applicant: Frederic Bancel ,  David Hely

Inventor： Frederic Bancel ,  David Hely

IPC: G06F7/38

CPC classification number: G01R31/31719 ,  G01R31/318536

Abstract: An electronic circuit includes configurable cells capable of being functionally linked to logic cells with which they cooperate to form at least one logic circuit if a chaining command signal is in a first (inactive) state. The electronic circuit also includes a logic interconnection circuit for performing the following functions if the chaining command signal is in a second (active) state. Functionally connecting the configurable cells in a linear feedback shift register if an authentication signal is in a first state, or functionally connecting the configurable cells in a chain in a predefined order to form a shift register if the authentication signal is in a second state.

Abstract translation: 电子电路包括能够在功能上与逻辑单元相连的可配置单元，如果链接命令信号处于第一（非活动）状态，则它们与它们协作形成至少一个逻辑电路。 如果链接命令信号处于第二（活动）状态，则电子电路还包括用于执行以下功能的逻辑互连电路。 如果认证信号处于第一状态，则功能地连接线性反馈移位寄存器中的可配置单元，或者如果认证信号处于第二状态，则以预定义顺序功能地连接链中的可配置单元以形成移位寄存器。

公开(公告)号：US07279977B2

公开(公告)日：2007-10-09

申请号：US11098005

申请日：2005-04-01

Applicant: Kuno Lenz

Inventor： Kuno Lenz

IPC: H03G3/12

CPC classification number: H03G1/0088 ,  H03H7/06

Abstract: An integrated circuit includes a resistive circuit with reduced mismatch that includes a primary resistive network with several main resistances (Rp) each having the same theoretical main value. It also includes an auxiliary resistance (Rau) having an auxiliary theoretical resistive value equal to the product or to the quotient of the theoretical main resistive value by √{square root over (2)}. All these resistances are connected together so as to attribute a theoretical overall resistive value to the primary resistive network equal to the theoretical auxiliary resistive value.

Abstract translation: 集成电路包括具有减小的失配的电阻电路，其包括具有几个主电阻（Rp）的主电阻网络，每个具有相同的理论主值。 它还包括辅助电阻（Rau），其具有等于产品的辅助理论电阻值或理论主电阻值的乘数乘以√{平方根超过（2.所有这些电阻连接在一起，以便归因于理论 与主电阻网络的总电阻值等于理论辅助电阻值。

公开(公告)号：US20070222613A1

公开(公告)日：2007-09-27

申请号：US11385458

申请日：2006-03-21

Applicant: Sylvain Fidelis ,  Pierre Rizzo

Inventor： Sylvain Fidelis ,  Pierre Rizzo

IPC: G08B13/14

CPC classification number: G06K19/07749 ,  G06K19/07718 ,  G06K19/07758 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for manufacturing an electronic tag to be affixed onto a product includes providing, in an electrically conductive film of a foil for packaging, packing or transporting the product, areas devoid of any electrically conductive material for delimiting in the electrically conductive film at least one antenna pattern for forming an antenna for an RFID tag. A semiconductor chip is connected to the antenna for forming an electronic tag.

Abstract translation: 用于制造要贴在产品上的电子标签的方法包括在用于包装，包装或运输产品的箔的导电膜中提供没有任何导电材料的区域，用于在导电膜中限定至少一个 用于形成用于RFID标签的天线的天线方向图。 半导体芯片连接到用于形成电子标签的天线。

公开(公告)号：US07269208B2

公开(公告)日：2007-09-11

申请号：US10088387

申请日：2001-07-11

Applicant: Simone Mazzoni ,  Héléne Came

Inventor： Simone Mazzoni ,  Héléne Came

IPC: H04B1/38 ,  H04L5/16

CPC classification number: H03M13/6508 ,  H03M13/2732 ,  H03M13/2782

Abstract: A device for sending/receiving digital data is capable of processing different bit rates from a group of predetermined bit rates. The device may include a channel coding/decoding stage including an interleaver, a deinterleaver, and a memory whose minimum size is fixed as a function of the maximum bit rate of the group of predetermined bit rates. The memory may have a first memory space assigned to the interleaver and a second memory space assigned to the deinterleaver. The size of each of the two memory spaces may be set as a function of the bit rate actually processed by the device.

Abstract translation: 用于发送/接收数字数据的设备能够处理来自一组预定比特率的不同比特率。 该设备可以包括信道编码/解码级，其包括交织器，解交织器和最小大小作为该组预定比特率的最大比特率的函数的固定的存储器。 存储器可以具有分配给交织器的第一存储器空间和分配给解交织器的第二存储器空间。 可以将两个存储空间中的每一个的大小设置为由该设备实际处理的比特率的函数。

公开(公告)号：US20070188237A1

公开(公告)日：2007-08-16

申请号：US11648104

申请日：2006-12-29

Applicant: David Chamla ,  Andreia Cathelin ,  Andreas Kaiser

Inventor： David Chamla ,  Andreia Cathelin ,  Andreas Kaiser

IPC: H03F3/68

CPC classification number: H03H11/1291 ,  H03F1/3211 ,  H03F3/19 ,  H03F3/211 ,  H03F3/602 ,  H03F2200/111

Abstract: An electronic device where the ratio between two amplification factors of two amplifiers, called main amplifiers, is adjusted using a control means. The control means constantly equalizes the output signals of the two main amplifiers by adapting one of the control signals. The output signals are acted on in order to adjust the control signals. Owing to the fact that the input signals are in a ratio N, this same ratio is obtained between the amplification factors of the two main amplifiers. The two main control signals, used to control the main amplifiers, are employed for controlling any other amplification factor of at least two other amplifiers or groups of amplifiers, so as to establish a ratio N between these other amplification factors. The main circuit thus allows N to be applied and regulated between the amplification factors of other amplifiers.

Abstract translation: 使用控制装置调整两个放大器的两个放大因子之间的比例，称为主放大器的电子装置。 控制装置通过调整一个控制信号来恒定地均衡两个主放大器的输出信号。 为了调整控制信号，输出信号。 由于输入信号为N的事实，在两个主放大器的放大系数之间获得相同的比例。 用于控制主放大器的两个主要控制信号用于控制至少两个其它放大器或放大器组的任何其它放大因子，以便建立这些其它放大因子之间的比率N. 因此，主电路允许在其他放大器的放大系数之间施加和调节N。

公开(公告)号：US07247928B2

公开(公告)日：2007-07-24

申请号：US10867277

申请日：2004-06-14

Applicant: Patrick Laurent ,  Xavier Baraton

Inventor： Patrick Laurent ,  Xavier Baraton

IPC: H01L23/495

CPC classification number: H01L21/563 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01094 ,  H01L2924/14

Abstract: Semiconductor device (1) and process for fabricating it, the device (1) including an electrical connection support plate (2), an integrated circuit chip placed at a certain location on the support plate (2) and placed at a certain distance from this support plate (2), a plurality of electrical connection balls connecting electrical connection regions (4) of the support plate (2) and corresponding electrical connection pads on the integrated circuit chip, and a fill material at least partly filling the space separating the chip from the plate, and in which the surface of the support plate (2), which has the electrical connection regions (4), is provided with an interlayer (6) made of an insulating material in which apertures (7) are provided above the electrical connection regions (4) and above complementary flow channels (9, 10).

Abstract translation: 半导体装置（1）及其制造方法，所述装置（1）包括电连接支撑板（2），集成电路芯片，放置在所述支撑板（2）上的特定位置并且放置在与所述支撑板 支撑板（2），连接支撑板（2）的电连接区域（4）和集成电路芯片上的对应电连接焊盘的多个电连接球，以及至少部分地填充分离芯片的空间的填充材料 并且其中具有电连接区域（4）的支撑板（2）的表面设置有由绝缘材料制成的中间层（6），其中孔（7）设置在该中间层 电连接区域（4）和上述互补流动通道（9,10）。

公开(公告)号：US07219297B2

公开(公告)日：2007-05-15

申请号：US10470441

申请日：2002-01-30

Applicant: Fabienne Dreville

Inventor： Fabienne Dreville

IPC: G06F11/00

CPC classification number: G11B20/10037 ,  G11B7/0906 ,  G11B20/1403 ,  H03L7/00

Abstract: A synchronization variable intended for a second clock signal is generated from a first clock signal and a phase variation signal. A first approximation of the second clock signal is determined, and other approximations close to the first approximation are also determined. An error is calculated for each of the approximations, and the best approximation is taken as the second clock signal.

Abstract translation: 从第一时钟信号和相位变化信号产生用于第二时钟信号的同步变量。 确定第二时钟信号的第一近似，并且还确定接近第一近似的其他近似。 对于每个近似值计算出一个误差，并将最佳近似作为第二个时钟信号。

公开(公告)号：US07215723B2

公开(公告)日：2007-05-08

申请号：US10239291

申请日：2001-03-20

Applicant: Pierre Rizzo ,  Francis Dell'Ova

Inventor： Pierre Rizzo ,  Francis Dell'Ova

IPC: H04L27/00

CPC classification number: G06K19/0701 ,  G06K7/0008 ,  G06K19/0723 ,  H03D1/10 ,  H03K5/082 ,  H04L25/061

Abstract: The invention concerns a demodulator of an amplitude-modulated signal (Vdb), characterised in that it comprises a peak detecting cell (DCR) capable of extracting the reference modulating signal (Vpeak1) of the modulated signal (Vdb); a first demodulator (FE) adapted to detect the peak of the reference modulating signal (Vpeak1) to generate a high comparison threshold and locate the start of the modulation, a second demodulator (RE) adapted to detect a trough of the reference modulating signal (Vpeak1) to generate a low comparison threshold and locate the end of the modulation; a logic processing unit capable of supplying the demodulated signal (Vdemod).

Abstract translation: 本发明涉及一种幅度调制信号（Vdb）的解调器，其特征在于它包括能够提取调制信号（Vdb）的参考调制信号（Vpeak 1）的峰值检测单元（DCR）; 适于检测参考调制信号（Vpeak 1）的峰值以产生高比较阈值并定位调制开始的第一解调器（FE），适于检测参考调制信号的谷值的第二解调器（RE） （Vpeak 1）产生低比较阈值并定位调制结束; 能够提供解调信号（Vdemod）的逻辑处理单元。

公开(公告)号：US20070094565A1

公开(公告)日：2007-04-26

申请号：US11534476

申请日：2006-09-22

Applicant: Laurent Paumier ,  Pascal Urard ,  Martial Comminges

Inventor： Laurent Paumier ,  Pascal Urard ,  Martial Comminges

IPC: H03M13/00

CPC classification number: H03M13/6505 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6566

Abstract: A system implemented for example in the form of an SoC comprises a first demodulator for generating a first data stream to be decoded, and a second demodulator for generating a second data stream to be decoded, and a block decoder. The block decoder comprises an input memory for storing blocks of data from the first data stream and blocks of data from the second data stream, and a block decoding unit for processing, from the input memory, the blocks of data from the first and second data streams.

Abstract translation: 以例如SoC形式实现的系统包括用于产生要解码的第一数据流的第一解调器和用于产生待解码的第二数据流的第二解调器和块解码器。 块解码器包括用于存储来自第一数据流的数据块和来自第二数据流的数据块的输入存储器，以及块解码单元，用于从输入存储器处理来自第一和第二数据的数据块 流。