公开(公告)号：US12169896B2

公开(公告)日：2024-12-17

申请号：US17489105

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey ,  Michael J. Mantor ,  Christopher J. Brennan ,  Mark M. Leather ,  Ryan James Cash

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.

公开(公告)号：US12169758B2

公开(公告)日：2024-12-17

申请号：US17491304

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Salonik Resch ,  Anthony Gutierrez ,  Yasuko Eckert ,  Vedula Venkata Srikant Bharadwaj ,  Mark H. Oskin

IPC: G06F9/48 ,  G06F11/36 ,  G06N10/00

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

公开(公告)号：US12169703B2

公开(公告)日：2024-12-17

申请号：US17205993

申请日：2021-03-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Ben-Moshe ,  Brian Kenneth Bennett ,  Qun Lin ,  David Ronald Oldcorn

IPC: G06F8/34 ,  G06F3/0482 ,  G06F3/04845 ,  G06F8/41 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for implementing graphics pipeline optimizations are disclosed. A user interface (UI) is generated to allow a user to analyze shaders and determine resource utilization on any of multiple different target graphic devices. The UI allows the user to manipulate the state associated with the target graphics device for a given graphics pipeline. After being edited by the user, the state of the graphics pipeline is converted into a textual representation and input into a meta-app. The meta-app creates an application programming interface (API) construct from the shader source code and textual representation of the state which is compiled by a driver component into machine-level instructions. Also, resource usage statistics are generated for a simulated run of the graphics pipeline on the target graphics device. Then, the machine-level instructions and resource usage statistics are displayed in the UI for the user to analyze.

公开(公告)号：US20240413035A1

公开(公告)日：2024-12-12

申请号：US18809578

申请日：2024-08-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： DAVID A. ROBERTS ,  GREG SADOWSKI ,  STEVEN RAASCH

IPC: H01L23/34 ,  G05B15/02 ,  G06F1/20 ,  H01L25/065

Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

公开(公告)号：US20240404167A1

公开(公告)日：2024-12-05

申请号：US18205174

申请日：2023-06-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad Ashkar ,  Manu Rastogi ,  Jing Ping

IPC: G06T15/00

Abstract: Techniques are described for implementing selective activation and deactivation of a dynamically allocated subset of shader engines, such as based on application-based profile information and/or on an active system power configuration. Instructions for execution are received from an application associated with a first application profile. Based on the application profile, a quantity of activated shader engines in a plurality of shader engines is modified. The quantity of activated shader engines is further modified responsive to receiving additional instructions from a second application, and/or to receiving one or more indications of an altered active system power configuration.

公开(公告)号：US20240403529A1

公开(公告)日：2024-12-05

申请号：US18326835

申请日：2023-05-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Richard Schultz ,  Omid Rowhani

IPC: G06F30/392 ,  G06F30/394 ,  H01L27/118

Abstract: An apparatus and method for efficiently creating layout of standard cells to improve floor planning of a chip. In various implementations, an integrated circuit uses multiple standard cells with an absence of diffusion breaks at cell boundaries. The standard cells use vertically stacked non-planer transistors. Multiple transistors are formed with an active region having a length between a source region and a drain region of a single transistor. Therefore, the active regions of these transistors are not formed across multiple gate terminals. By having active regions of these transistors formed across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between two active regions of the two adjoining standard cells. This is true even when the two adjoining standard cells share a source/drain region at the cell boundaries. Accordingly, forming diffusion breaks at the edges of these standard cells can be skipped.

公开(公告)号：US20240395289A1

公开(公告)日：2024-11-28

申请号：US18671854

申请日：2024-05-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh ADHINARAYANAN ,  Hyung-Dong LEE ,  Bradford BECKMANN ,  Seyedmohammad SEYEDZADEHDELCHEH ,  Sergey BLAGODUROV

IPC: G11C5/02 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Integrated circuit (IC) memory devices and methods for fabricating the same are provided. In one example, an integrated circuit (IC) memory device is provided that includes a substrate, at least two or more memory (IC) dies, and a non-memory IC die integrated in a chip package. The memory (IC) dies are stacked on the substrate to form a memory die stack. The non-memory IC die contains row segmentation logic having an output routed to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.

公开(公告)号：US20240393861A1

公开(公告)日：2024-11-28

申请号：US18540703

申请日：2023-12-14

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Josip Popovic ,  Rashad Oreifej ,  Robert Alan Marc Gottlieb

IPC: G06F1/3296 ,  G06T15/00

Abstract: An apparatus and method for efficiently managing voltage transients on a power rail caused by current transients of an integrated circuit. In various implementations, a computing system includes a processing circuit that executes instructions of a compiler that includes a current transients mitigator. When executing the instructions of the current transients mitigator, the processing circuit generates an estimate of a time rate of current flow being drawn from or returned to the power rail based on instruction types of a first sequence of instructions. Based on the estimate exceeds a threshold, the processing circuit replaces the first sequence of instructions with a second sequence of instructions that provides a smaller estimate. The second sequence is issued to the one or more compute circuits that utilize the power rail, rather than the first sequence.

公开(公告)号：US12153958B2

公开(公告)日：2024-11-26

申请号：US18045128

申请日：2022-10-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US12153957B2

公开(公告)日：2024-11-26

申请号：US17957714

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

IPC: G06F9/48

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.