公开(公告)号：US20080181294A1

公开(公告)日：2008-07-31

申请号：US11701164

申请日：2007-01-31

Applicant: Jiri Andrle ,  Jan Ingerle ,  Petr Kopecky

Inventor： Jiri Andrle ,  Jan Ingerle ,  Petr Kopecky

IPC: H03K7/04

CPC classification number: H04B1/1027 ,  H03J5/242

Abstract: A system and method to optimize the quality of a modulated signal. In one aspect, an AM demodulator is used in conjunction with proper bandwidth selection of an FM signal. For example, the AM demodulator can be used to generate an instantaneous absolute value of the FM signal. The average value of the FM signal over a period of time is subtracted from the instantaneous absolute value in order to determine a variance in amplitude in the FM signal. In another aspect, several filters may be tested and the one having the lowest variance in amplitude may be used in order to select the filter having the desirable bandwidth.

Abstract translation: 一种优化调制信号质量的系统和方法。 在一个方面，AM解调器与FM信号的适当带宽选择结合使用。 例如，AM解调器可用于产生FM信号的瞬时绝对值。 为了确定FM信号中的幅度方差，从瞬时绝对值中减去一段时间内的FM信号的平均值。 在另一方面，可以测试几个滤波器，并且可以使用具有最小幅度变化的滤波器，以便选择具有期望带宽的滤波器。

公开(公告)号：US20070170974A1

公开(公告)日：2007-07-26

申请号：US11655774

申请日：2007-01-19

Applicant: Hynek Saman ,  Peter Murin ,  Martin Boksa ,  Pavel Panus

Inventor： Hynek Saman ,  Peter Murin ,  Martin Boksa ,  Pavel Panus

IPC: G06G7/12

CPC classification number: H03F3/45928 ,  H03F3/45475 ,  H03F2200/459 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03F2203/45522 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45586 ,  H03F2203/45591 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03G1/0088

Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.

Abstract translation: 一种电路，包括第一敏感节点，连接在第一敏感节点和第一开关的第一终端之间的第一组件，所述第一开关由在电源电压电平和第二电压电平之间变化的第一控制信号控制， 开关，包括连接到所述第一开关的第一端子的第一端子和连接到清洁电压源的第二端子，所述第二开关被控制为当所述第一开关处于所述第一开关时将所述第一开关的第一节点连接到所述清洁电压源 非导电状态。

公开(公告)号：US20240125930A1

公开(公告)日：2024-04-18

申请号：US18377893

申请日：2023-10-09

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics (Alps) SAS

Inventor： Robin VASSAL ,  Jiri ANDRLE ,  Peter CABAJ ,  Cyrille TROUILLEAU

IPC: G01S17/08 ,  G01S7/497

CPC classification number: G01S17/08 ,  G01S7/497

Abstract: A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.

公开(公告)号：US11734221B2

公开(公告)日：2023-08-22

申请号：US17199418

申请日：2021-03-11

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Rolf Nandlinger ,  Radek Olexa

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F9/30134 ,  G06F13/1673 ,  G06F13/4031

Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.

公开(公告)号：US20230171529A1

公开(公告)日：2023-06-01

申请号：US17537263

申请日：2021-11-29

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Tomas TEPLY ,  Karel BLAHA

IPC: H04R1/10 ,  H04R9/04 ,  H04R9/06

CPC classification number: H04R1/1025 ,  H04R9/04 ,  H04R9/06 ,  H04R1/1075 ,  H04R2420/07

Abstract: The present disclosure is directed to a device that includes a headphone speaker housing that includes a coil having a first terminal and a second terminal that is configured to operate in a sound generation mode and a battery charging mode. A class D amplifier circuit is configured to rectify in a battery charging mode and amplify in a sound generation mode, the class D amplifier is coupled to the first terminal and the second terminal of the coil. The class D amplifier including a first, second, third, and fourth switch, the first terminal coupled between the first and second switch, the second terminal coupled between the third and fourth switch. An audio generation circuit having a third terminal and a fourth terminal, the third terminal coupled between the first and third switch of the class D amplifier and the fourth terminal coupled between the second and fourth switch of the class D amplifier. A battery charging circuit coupled to the third terminal and the fourth terminal.

公开(公告)号：US20220286319A1

公开(公告)日：2022-09-08

申请号：US17677113

申请日：2022-02-22

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: H04L12/403 ,  G06F9/30

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

公开(公告)号：US11366778B2

公开(公告)日：2022-06-21

申请号：US16874055

申请日：2020-05-14

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20220109375A1

公开(公告)日：2022-04-07

申请号：US17490793

申请日：2021-09-30

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Design and Application S.R.O.

Inventor： Alberto IORIO ,  Maurizio FORESTA ,  Emilio VOLPI ,  Jan NOVOTNY

IPC: H02M3/335 ,  G01R19/165 ,  H02M3/00 ,  H02M1/00

Abstract: A synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. A second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and a third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant in which the measured voltage reaches a first threshold value and a switch-off instant in which the measured voltage reaches a second threshold value. The synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal as a function of the measured voltage.

公开(公告)号：US20220069626A1

公开(公告)日：2022-03-03

申请号：US17008238

申请日：2020-08-31

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Tomas Teply

IPC: H02J50/12 ,  H02J7/02 ,  H02J50/70 ,  H02J50/80 ,  H02J50/00 ,  H01F38/14 ,  H01F27/28 ,  H01F27/36 ,  H02J50/40 ,  H04R1/10

Abstract: A system and method for wireless charging a wireless earbud. The wireless earbud having a body that includes a passive magnetic shield and a coil. The coil is wound around a portion of the body comprising the passive magnetic shielding. The wireless earbud receiving wireless energy in response to the placement of the body within an electromagnetic field, which results in the charging of a battery of the wireless earbud.

公开(公告)号：US11082018B2

公开(公告)日：2021-08-03

申请号：US16786182

申请日：2020-02-10

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Sandor Petenyi

IPC: H03F3/45 ,  H03F1/02 ,  H03F1/30

Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.