公开(公告)号：US07865787B2

公开(公告)日：2011-01-04

申请号：US11721010

申请日：2005-12-09

申请人： Holger Haberla ,  Soeren Lohbrandt

发明人： Holger Haberla ,  Soeren Lohbrandt

IPC分类号： G11C29/00 ,  G01R31/28 ,  G01R31/02 ,  G01R31/26 ,  G01R31/36

CPC分类号： G01R31/31721 ,  G01R31/3185 ,  G01R31/318575

摘要： Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.

摘要翻译： 公开了一种用于测试作为位于半导体晶片上的整个电路的一部分的嵌入式电路的布置。 公开了一种集成半导体装置，其包括具有输入和输出（7）的整个电路（8），作为整个电路（8）的一部分的嵌入式电路（1），并且配备有不直接连接的嵌入式输入和输出 到整个电路（8）的输入和输出（7）; 测试电路（2,5,6），其连接到嵌入式输入和输出端，以便在测试阶段期间馈送和读出信号。 提供单独的电源电压连接（3），其独立于整个电路（8）的电源电压分别供应嵌入式电路（1）和测试电路（2,5,6），使得输入 整个电路不需要连接用于测试嵌入式电路，而只有测试嵌入式电路绝对不可或缺的输入和输出需要连接到测试系统。

公开(公告)号：US20100301483A1

公开(公告)日：2010-12-02

申请号：US12740554

申请日：2008-10-30

申请人： Daniel Gaebler

发明人： Daniel Gaebler

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L27/14623 ,  H01L27/14685 ,  H01L27/14818 ,  H01L31/02164 ,  H01L31/0236 ,  Y02E10/50

摘要： In an integrated circuit, a light sensitive area is protected against radiation by arranging a light blocking layer sequence (504) on top of the light sensitive area. The light blocking layer sequence comprises one or several metal layers (504a) and a silicon layer (503b, 1) for the purpose of absorption. A moth eye structure is provided on the silicon layer. Thereby, a radiation incident by reflection is minimized in such a way that also stray light can effectively be kept from the light sensitive area below the light blocking layer sequence (504).

摘要翻译： 在集成电路中，通过在光敏区域的顶部布置遮光层序列（504）来保护光敏区域免受辐射。 遮光层序列包括一个或多个金属层（504a）和用于吸收的硅层（503b，1）。 在硅层上设置有蛾眼结构。 因此，通过反射入射的辐射以这样的方式被最小化，使得杂光可以有效地从光阻挡层序列（504）下方的光敏区域保持。

公开(公告)号：US20100295124A1

公开(公告)日：2010-11-25

申请号：US12304789

申请日：2007-06-14

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7824 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/7823 ,  H01L29/7835

摘要： It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.

摘要翻译： 本发明的目的是提供一种保证尽可能高的电压的MOS晶体管（20），其具有尽可能小的所需面积，并且能够集成到集成的智能电力电路中。 由于本发明的目的是形成晶体管的边缘结构，因此它确实满足了对高穿透电压的要求，对周围区域的良好隔离以及硅片上的最小表面。 这是通过具有用于高于100V的高额定电压的漏极（30）和源极（28）的细长MOS功率晶体管实现的，其中晶体管包括在边缘区域中的隔离沟槽（22），用于防止在额定电压之下的早期电气突破 。 沟槽衬有隔离材料（70,72），其中隔离沟槽终止电路部件。

公开(公告)号：US20100252880A1

公开(公告)日：2010-10-07

申请号：US12669728

申请日：2008-07-18

申请人： Paul Ronald Stribley

发明人： Paul Ronald Stribley

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/22 ,  H01L29/06 ,  H01L21/336 ,  H01L21/24

CPC分类号： H01L21/266 ,  H01L23/5252 ,  H01L28/20 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7391 ,  H01L29/7833 ,  H01L29/7836 ,  H01L29/7838 ,  H01L29/78621 ,  H01L29/8611 ,  H01L29/872 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region.A device comprises a semiconductor layer (6); a first doped region (5) within the semiconductor layer; a second doped region (7) within the first doped region (5); and a silicon layer (9) disposed over a part of the semiconductor layer; wherein the silicon layer is disposed over a part of the first doped region (5) but not over the second doped region (7).

摘要翻译： 制造半导体器件的方法包括以下步骤：顺序地：沉积第一硅层; 图案化第一硅层以获得第一硅区; 将第一掺杂剂注入第一硅区域的第一部分中，使用第一掩模限定第一硅区域的第一部分; 沉积第二硅层; 图案化第二硅层以获得第二硅区; 以及将第二掺杂剂注入到所述第一硅区域的第二部分中，所述第一硅区域的第二部分由所述第一掩模和所述第二硅区域限定。 一种器件包括半导体层（6）; 半导体层内的第一掺杂区域（5）; 在所述第一掺杂区域（5）内的第二掺杂区域（7）; 以及设置在半导体层的一部分上的硅层（9） 其中所述硅层设置在所述第一掺杂区域（5）的一部分上方，但不设置在所述第二掺杂区域（7）上。

公开(公告)号：US20100155910A1

公开(公告)日：2010-06-24

申请号：US12305092

申请日：2007-06-16

申请人： Daniel Gaebler

发明人： Daniel Gaebler

IPC分类号： H01L31/0216 ,  H01L31/18 ,  H01L21/31 ,  H01L21/302

CPC分类号： H01L27/1462 ,  H01L27/14685 ,  H01L31/02165

摘要： The invention refers to an efficient process for selectively rendering a semiconductor surface antireflective which is part of integrated circuits. The antireflective effect is based interference effects of a simple layer or a layer system. For example, an oxide layer and super-imposed silicon nitride layer form the system, wherein the silicon nitride layer is deposited in an earlier phase of the fabrication of the integrated circuit as a protective layer (“silicide block layer”) and also serves as an etch stop layer for the optical window.

摘要翻译： 本发明涉及一种用于选择性地渲染作为集成电路的一部分的半导体表面抗反射的有效方法。 抗反射效应是简单层或层系统的干扰效应。 例如，氧化物层和超级氮化硅层形成系统，其中氮化硅层以制造集成电路的较早阶段作为保护层（“硅化物阻挡层”）沉积，并且还用作 用于光学窗口的蚀刻停止层。

公开(公告)号：US20090250724A1

公开(公告)日：2009-10-08

申请号：US11721717

申请日：2005-12-14

申请人： John Nigel Ellis

发明人： John Nigel Ellis

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/7378

摘要： A bipolar transistor is formed on a heavily doped silicon substrate (1). An epitaxially grown collector (12) is formed on the substrate (1) and comprises silicon containing germanium at least at the top of the collector (12). An epitaxial base (13) is formed on the collector (12) to have the opposite polarity and also comprises silicon containing germanium at least at the bottom of the base (13). An emitter is formed at the top of the base (13) and comprises polysilicon doped to have the same polarity as the collector (12).

摘要翻译： 在重掺杂硅衬底（1）上形成双极晶体管。 在衬底（1）上形成外延生长的收集器（12），并且至少在收集器（12）的顶部包括含硅的锗。 在集电器（12）上形成具有相反极性的外延基极（13），并且至少在基底（13）的底部还包含含硅的锗。 发射极形成在基极（13）的顶部并且包括被掺杂以具有与集电极（12）相同极性的多晶硅。

公开(公告)号：US20090180188A1

公开(公告)日：2009-07-16

申请号：US12294129

申请日：2007-03-23

申请人： Konrad Bach ,  Daniel Gaebler

发明人： Konrad Bach ,  Daniel Gaebler

IPC分类号： G02B1/11 ,  G02B5/30

CPC分类号： G02B1/118 ,  G02B1/11

摘要： Methods and optical devices are proposed, which comprise a nanostructure (4) on a curved surface so that a broadband antireflective characteristic is obtained. The nanostructure is fabricated by means of a self-masking single step etch process of silicon (3) on the curved surface

摘要翻译： 提出了在曲面上包含纳米结构（4）的方法和光学装置，从而获得宽带抗反射特性。 通过硅（3）在弯曲表面上的自掩蔽单步蚀刻工艺制造纳米结构

公开(公告)号：US07535074B2

公开(公告)日：2009-05-19

申请号：US10534304

申请日：2003-11-12

申请人： Wolfgang Einbrodt ,  Horst Zimmermann ,  Michael Foertsch

发明人： Wolfgang Einbrodt ,  Horst Zimmermann ,  Michael Foertsch

IPC分类号： H01L29/868

CPC分类号： H01L31/1055 ,  H01L31/105

摘要： The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the pin photodiode is formed by combining a low doped first p-epitaxial layer, which has maximum thickness and doping concentration, placed upon a particularly high doped p substrate, with a low doped second n− epitaxial layer that borders the first layer, and n+ cathode of the pin photodiode being integrated into the second layer. The p areas delimit the second n epitaxial layer in a latent direction while another anode connecting area of the pin diode is provided on the rear face in addition to the anode connection.

摘要翻译： 本发明涉及一种按照BiCMOS技术生产的单片集成垂直pin光电二极管，它包括一个面向光的平面，以及位于光电二极管顶面上的p个区域的背面和阳极连接。 引脚光电二极管的i区通过将具有最大厚度和掺杂浓度的低掺杂的第一p外延层组合在一个特别高掺杂的p衬底上，与低掺杂的第二n-外延层接合 第一层，并且pin光电二极管的n +阴极集成到第二层中。 p区域在潜在方向上限定第二n外延层，除了阳极连接之外，还在背面设置pin二极管的另一个阳极连接区域。

公开(公告)号：US20080283960A1

公开(公告)日：2008-11-20

申请号：US11908269

申请日：2006-03-10

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L21/743 ,  H01L21/76229 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a method for producing structures which make it possible to form a trench insulation and to bring into contact SOI wafers provided with active thick layers and which are easily processable. For this purpose, a carrier wafer electric contact and the insulation trench are provided with components exhibiting high-blocking capability of insertion into an integrated circuit SOI wafer. A narrow trench for an insulating trench (8) and a large trench for a carrier wafer contact (9) are etched up to an insulating oxide layer (2) and are buried by a masking layer which is thicker than the buried oxide layer (2). In the large trench (9), a polysilicon spacer (12) remains on the sidewalls, respectively, in the form of a predeposited polysilicon layer (11) rest. The adjustment of the polysilicon etching makes it possible to obtain the spacer (12) provided with a desired height. At least buried oxide (2, 10) is removed by etching from the bottom of the large trench (9) in such a way that a residual oxide layer (13) remains on the surface. The deposition of a second electrically conductive filling layer (14) fills also a large insulating trench (19).

摘要翻译： 本发明涉及一种用于制造结构的方法，其可以形成沟槽绝缘体并且使与具有活性厚层的SOI晶片接触并且易于加工。 为此，载体晶片电接触和绝缘沟槽具有插入到集成电路SOI晶片中的高阻挡能力的部件。 用于绝缘沟槽（8）和用于载体晶片接触（9）的大沟槽的窄沟槽被蚀刻到绝缘氧化物层（2），并被掩埋层掩埋，掩模层比掩埋氧化物层（2 ）。 在大沟槽（9）中，多晶硅间隔物（12）分别以预沉积的多晶硅层（11）的形式分别保留在侧壁上。 多晶硅蚀刻的调整使得可以获得具有期望高度的间隔物（12）。 至少掩埋氧化物（2,10）通过从大沟槽（9）的底部进行蚀刻而被去除，使得剩余的氧化物层（13）保留在表面上。 第二导电填充层（14）的沉积也填充有大的绝缘沟槽（19）。

公开(公告)号：US20080243443A1

公开(公告)日：2008-10-02

申请号：US11576736

申请日：2005-10-05

申请人： Ralf Lerner ,  Wolfgang Miesch

发明人： Ralf Lerner ,  Wolfgang Miesch

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

摘要： A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

摘要翻译： 一种用于设计具有指定设计功率电平的第一垂直MOS功率晶体管的方法。 该方法包括以下步骤：将垂直MOS功率晶体管的布局组合成至少部分不同的布局部分，每个部分具有已知的设计数据，部分包括至少一个第一布局部分，其包括 给定数量的单晶体管单元，并且通过使用部件的已知设计数据并且基于部件的布局组合来调整第一垂直MOS功率晶体管的指定设计功率电平。