公开(公告)号：US20120187461A1

公开(公告)日：2012-07-26

申请号：US13499446

申请日：2009-09-30

Applicant: Wolfgang Einbrodt ,  Daniel Gaebler

Inventor： Wolfgang Einbrodt ,  Daniel Gaebler

IPC: H01L31/113 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L21/823475 ,  H01L27/14618 ,  H01L31/02005 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/1136 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.

Abstract translation: 基于用作有效的抗蚀剂层的栅极结构来制造半导体部件中的窗口，以便可靠地蚀刻绝缘层堆叠而不暴露光敏半导体区域。 然后基于已建立的栅极蚀刻工艺去除栅极结构中的多晶硅，栅极绝缘层保持光敏半导体材料的完整性。

公开(公告)号：US20090001434A1

公开(公告)日：2009-01-01

申请号：US11718364

申请日：2005-11-03

Applicant: Konrad Bach ,  Wolfgang Einbrodt

Inventor： Konrad Bach ,  Wolfgang Einbrodt

IPC: H01L27/146 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/105 ,  H01L27/14601

Abstract: The invention relates to a fast photodiode and to a method for the production thereof in CMOS technology. The integrated PIN photodiode, which is formed or can be formed by CMOS technology, consists of an anode corresponding to a highly doped p-type substrate with a specific electric resistance of less than 50 mOhm*cm, a lightly p-doped l-region which is adjacent to the anode, and an n-type cathode which corresponds to the doping in the n-well region. The lightly doped l-region has a doping concentration of less than 1014 cm−3 and has a thickness of between 8 and 25 μm. The cathode region is completely embedded in the very lightly doped l-region. A distance from the edge of the cathode region to a highly doped adjacent region is in the range of 2.5 μm to 10 μm.

Abstract translation: 本发明涉及一种快速光电二极管及其在CMOS技术中的制造方法。 由CMOS技术形成或可以形成的集成PIN光电二极管由对应于具有小于50mOhm * cm的比电阻的高掺杂p型衬底的阳极组成，轻掺杂的p型区域 其与阳极相邻，以及对应于n阱区域中的掺杂的n型阴极。 轻掺杂的1-区具有小于1014cm-3的掺杂浓度，并且具有在8和25μm之间的厚度。 阴极区域完全嵌入非常轻掺杂的l区域。 从阴极区域的边缘到高度掺杂的相邻区域的距离在2.5μm到10μm的范围内。

公开(公告)号：US08865553B2

公开(公告)日：2014-10-21

申请号：US13499446

申请日：2009-09-30

Applicant: Wolfgang Einbrodt ,  Daniel Gaebler

Inventor： Wolfgang Einbrodt ,  Daniel Gaebler

IPC: H01L21/3213 ,  H01L27/146 ,  H01L21/8234

CPC classification number: H01L31/02327 ,  H01L21/823475 ,  H01L27/14618 ,  H01L31/02005 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/1136 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.

Abstract translation: 基于用作有效的抗蚀剂层的栅极结构来制造半导体部件中的窗口，以便可靠地蚀刻绝缘层堆叠而不暴露光敏半导体区域。 然后基于已建立的栅极蚀刻工艺去除栅极结构中的多晶硅，栅极绝缘层保持光敏半导体材料的完整性。

公开(公告)号：US07491925B2

公开(公告)日：2009-02-17

申请号：US10596035

申请日：2004-12-06

Applicant: Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

Inventor： Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

IPC: H03F3/08

CPC classification number: H01L27/144 ,  H01L31/02016 ,  H01L31/022408 ,  H01L31/10

Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evaluation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.

Abstract translation: 本发明的目的是配置光电检测器（10），使得在现有技术中已知的检测器上特别是当对评估电子器件进行单片整合时，不会产生用于处理低发光强度的缺点。 所述目的通过用于处理低发光强度的光电检测器实现，其包括单片集成跨阻抗放大器和单片集成评估电子器件。 实际的光电池组件（20）被分配给光优选落在其上的芯片面。 电子电路部件（30）布置在相对的芯片面上。 在光电管和电子电路之间的电连接（40）在垂直于芯片法线的方向上具有延伸。

公开(公告)号：US20070018268A1

公开(公告)日：2007-01-25

申请号：US10534304

申请日：2003-11-12

Applicant: Wolfgang Einbrodt ,  Horst Zimmerman ,  Michael Foertsch

Inventor： Wolfgang Einbrodt ,  Horst Zimmerman ,  Michael Foertsch

IPC: H01L31/00 ,  H01L21/00

CPC classification number: H01L31/1055 ,  H01L31/105

Abstract: The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the pin photodiode is formed by combining a low doped first p-epitaxial layer, which has maximum thickness and doping concentration, placed upon a particularly high doped p substrate, with a low doped second n− epitaxial layer that borders the first layer, and n+ cathode of the pin photodiode being integrated into the second layer. The p areas delimit the second n epitaxial layer in a latent direction while another anode connecting area of the pin diode is provided on the rear face in addition to the anode connection.

Abstract translation: 本发明涉及一种按照BiCMOS技术生产的单片集成垂直pin光电二极管，它包括一个面向光的平面，以及位于光电二极管顶面上的p个区域的背面和阳极连接。 引脚光电二极管的i区通过将具有最大厚度和掺杂浓度的低掺杂第一p外延层组合在一个特别高掺杂的p衬底上，其中掺杂第二p型外延层具有低掺杂的第二p型外延层， SUP→外延层，其与引脚光电二极管的第一层接合，并且第二层中的引脚光电二极管的n + p区域在潜在方向上限定第二n外延层，除了阳极连接之外，还在背面设置pin二极管的另一个阳极连接区域。

公开(公告)号：US07535074B2

公开(公告)日：2009-05-19

申请号：US10534304

申请日：2003-11-12

Applicant: Wolfgang Einbrodt ,  Horst Zimmermann ,  Michael Foertsch

Inventor： Wolfgang Einbrodt ,  Horst Zimmermann ,  Michael Foertsch

IPC: H01L29/868

CPC classification number: H01L31/1055 ,  H01L31/105

Abstract: The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the pin photodiode is formed by combining a low doped first p-epitaxial layer, which has maximum thickness and doping concentration, placed upon a particularly high doped p substrate, with a low doped second n− epitaxial layer that borders the first layer, and n+ cathode of the pin photodiode being integrated into the second layer. The p areas delimit the second n epitaxial layer in a latent direction while another anode connecting area of the pin diode is provided on the rear face in addition to the anode connection.

Abstract translation: 本发明涉及一种按照BiCMOS技术生产的单片集成垂直pin光电二极管，它包括一个面向光的平面，以及位于光电二极管顶面上的p个区域的背面和阳极连接。 引脚光电二极管的i区通过将具有最大厚度和掺杂浓度的低掺杂的第一p外延层组合在一个特别高掺杂的p衬底上，与低掺杂的第二n-外延层接合 第一层，并且pin光电二极管的n +阴极集成到第二层中。 p区域在潜在方向上限定第二n外延层，除了阳极连接之外，还在背面设置pin二极管的另一个阳极连接区域。

公开(公告)号：US20070164393A1

公开(公告)日：2007-07-19

申请号：US10596035

申请日：2004-12-06

Applicant: Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

Inventor： Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

IPC: H01L29/00

CPC classification number: H01L27/144 ,  H01L31/02016 ,  H01L31/022408 ,  H01L31/10

Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evalation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.

Abstract translation: 本发明的目的是配置光电检测器（10），使得在现有技术中已知的检测器上特别是当对评估电子器件进行单片整合时，不会产生用于处理低发光强度的缺点。 所述目的通过用于处理低发光强度的光电检测器实现，其包括单片集成跨阻抗放大器和单片集成评估电子器件。 实际的光电池组件（20）被分配给光优选落在其上的芯片面。 电子电路部件（30）布置在相对的芯片面上。 在光电管和电子电路之间的电连接（40）在垂直于芯片法线的方向上具有延伸。