公开(公告)号：US08278183B2

公开(公告)日：2012-10-02

申请号：US12670771

申请日：2008-07-25

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L21/76

CPC分类号： H01L21/76264 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/76237

摘要： A description is given of a method for producing isolation trenches (32, 34) with different sidewall dopings on a silicon-based substrate wafer for use in the trench-isolated smart power technology. In this case, a first trench (32) having a first width and a second trench (34) having a second width which is greater than the first width are formed using a hard mask (30). The sidewalls of the first and second trenches are doped in accordance with a first doping type in order to produce sidewalls having a first doping. A material layer (50, 51, 60, 61) is deposited with a thickness determined so as to fill the first trench (32) completely up to and beyond the hard mask and to maintain the gap (34a) in the second trench (34). By means of isotropic etching the material layer is removed from the second trench, but residual material of the material layer is maintained in the first trench. A further doping of sidewalls of the first trench or of the second trench in the presence of the residual material is then performed.

摘要翻译： 给出了在用于沟槽隔离智能电力技术的硅基衬底晶片上制造具有不同侧壁掺杂的隔离沟槽（32,34）的方法的描述。 在这种情况下，使用硬掩模（30）形成具有第一宽度的第一沟槽（32）和具有大于第一宽度的第二宽度的第二沟槽（34）。 第一和第二沟槽的侧壁根据第一掺杂类型被掺杂，以便产生具有第一掺杂的侧壁。 沉积材料层（50,51,60,61），其厚度确定为将第一沟槽（32）完全填充到硬掩模之上并超过硬掩模，并且将间隙（34a）保持在第二沟槽（34）中 ）。 通过各向同性蚀刻，从第二沟槽去除材料层，但材料层的剩余材料保持在第一沟槽中。 然后在存在残余材料的情况下进一步掺杂第一沟槽或第二沟槽的侧壁。

公开(公告)号：US20120098084A1

公开(公告)日：2012-04-26

申请号：US12999658

申请日：2009-06-19

申请人： Ralf Lerner ,  Uwe Eckoldt

发明人： Ralf Lerner ,  Uwe Eckoldt

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76264

摘要： A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

摘要翻译： 一种半导体元件，其具有形成在半导体材料中的直的绝缘沟槽，从而提供横向绝缘的半导体区域。 每个绝缘沟槽沿着由中心线表示的纵向方向具有均匀的宽度。 半导体部件具有交叉区域，至少三个直的绝缘沟槽引导到该相交区域。 相交区域的中心被定义为中心线的连续点的交点。 设置在交叉区域的中央半导体区域与半导体区域中的一个连接并且包含交叉区域的中心。

公开(公告)号：US07598098B2

公开(公告)日：2009-10-06

申请号：US10553470

申请日：2004-04-16

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L21/76229 ,  H01L21/76232

摘要： The aim of the invention is to create a simple monitoring or testing method for monitoring a reduction in thickness as material is removed from a bonded semiconductor wafer pair, which prevents failure effects as material is removed from wafers (polishing, grinding or lapping). In addition, the costs of the material removal process should be reduced by minimizing the complexity of monitoring, as well as by reducing the amount of resulting refuse. To this end, the invention provides a test structure (4, 5, 6, 7, 8, 9) comprised of a systematic row of a number of different depth trenches that are made in the (active) wafer (2). A thickness (h6; h7) of the active wafer (2) desired during material removal, particularly during a polishing, corresponds to the depth (t6; t7) of a reference trench (6; 7) of the trenches of the test structure, said reference trench (6) being surrounded by flatter and deeper trenches (5, 7). The active wafer (2), via the side (2a) on which the test structure was provided, is bonded to the second wafer of the semiconductor wafer pair provided as a supporting wafer (1). A removal of material, particularly a polishing, is effected on the rear (2b) of the active wafer (2) until the reference trench (6) is exposed. The result is visually observed (30) in order to monitor the reduction in thickness as material is removed from the first wafer (2).

摘要翻译： 本发明的目的是创建一种简单的监测或测试方法，用于监测从结合的半导体晶片对去除材料时的厚度减小，从而防止材料从晶片（抛光，研磨或研磨）中移除时的失效效应。 此外，应通过最小化监测的复杂性以及减少垃圾的数量来减少材料清除过程的成本。 为此，本发明提供了由（活性）晶片（2）中制成的多个不同深度沟槽的系统行组成的测试结构（4,5,6,7,8,9）。 在材料去除期间，特别是在抛光过程中期望的活性晶片（2）的厚度（h6; h7）对应于测试结构的沟槽的参考沟槽（6; 7）的深度（t6; t7） 所述参考沟槽（6）被较平坦和较深的沟槽（5,7）包围。 通过设置有测试结构的侧面（2a）将活性晶片（2）接合到设置为支撑晶片（1）的半导体晶片对的第二晶片上。 在活性晶片（2）的后部（2b）上实现去除材料，特别是抛光，直到参考沟槽（6）暴露。 目视观察结果（30），以便在材料从第一晶片（2）移除时监测厚度的减小。

公开(公告)号：US20080290366A1

公开(公告)日：2008-11-27

申请号：US11629022

申请日：2005-06-10

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L29/739 ,  H01L29/861

CPC分类号： H01L29/7398 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/861

摘要： An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.

摘要翻译： SOI器件包括限定垂直漂移区的隔离沟槽，隔离沟槽所延伸的掩埋绝缘层，以及用于发射邻近绝缘层形成并与漂移区接触的电荷载流子的电极区域。 电极区域包括具有第一类型掺杂的第一条形部分和具有与第一类型掺杂相反的第二类型掺杂的第二条形部分。 在隔离沟槽的第一侧壁处提供第一类型掺杂的第一侧壁掺杂，并且在隔离沟槽的第二侧壁处提供第二类型的掺杂的第二侧壁掺杂。 第一条形部分与第一侧壁掺杂接触，第二条形部分与第二侧壁掺杂接触。

公开(公告)号：US20070054422A1

公开(公告)日：2007-03-08

申请号：US10552984

申请日：2004-04-19

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L21/66 ,  G01L21/30 ,  H01L21/302

CPC分类号： H01L22/34

摘要： The aim of the invention is to discover a simple to implement and reliable recognition of the moment at which insulation trenches reach the buried insulating layer during an etch process. The technological reliability during the etching of these trenches should be increased, the production of refuse should be prevented, and costs should be reduced. To these ends, the invention provides a test structure for verifying an insulation trench etching in an SOI wafer. After an etching o insulation trenches, this test structure has a row of connected islands, whereby each island is surrounded by a trench. This trench has a different width form island to island (A, B; B, C) while including a trench width that appears the form of an insulation trench in an active circuit. A section of the surrounding trench (a, b) of each island (A, B) forms a common piece with the trench of adjacent islands. The respective section has, in the inner islands, the width of the adjacent trench having the next larger or the next smaller measure of width in the row.

摘要翻译： 本发明的目的是发现在蚀刻过程中绝缘沟槽到达掩埋绝缘层的时刻的简单实现和可靠的识别。 在这些沟槽蚀刻过程中的技术可靠性要提高，防止垃圾的生产，降低成本。 为此，本发明提供了一种用于验证SOI晶片中的绝缘沟槽蚀刻的测试结构。 在蚀刻绝缘沟槽之后，该测试结构具有一排连接的岛，由此每个岛被沟槽包围。 该沟槽具有岛到岛的不同宽度（A，B; B，C），同时包括在有源电路中出现绝缘沟槽形式的沟槽宽度。 每个岛屿（A，B）的周围沟槽（a，b）的一部分与相邻岛屿的沟槽形成共同的部分。 相应的部分在内岛中具有相邻沟槽的宽度，该宽度具有下一个较大的或下一个较小的宽度尺寸。

公开(公告)号：US08921945B2

公开(公告)日：2014-12-30

申请号：US12999028

申请日：2009-06-15

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/7394 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/7803 ,  H01L29/7812

摘要： The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 μm. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.

摘要翻译： 功率晶体管被配置为集成到具有约50μm的厚度的活性硅层的沟槽隔离厚层SOI技术中。 功率晶体管可能具有比DMOS晶体管更低的电阻，并且具有比IGBT更快的关断特性。

公开(公告)号：US08823095B2

公开(公告)日：2014-09-02

申请号：US12304789

申请日：2007-06-14

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7824 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/7823 ,  H01L29/7835

摘要： It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.

摘要翻译： 本发明的目的是提供一种保证尽可能高的电压的MOS晶体管（20），其具有尽可能小的所需面积，并且能够集成到集成的智能电力电路中。 由于本发明的目的是形成晶体管的边缘结构，因此它确实满足了对高穿透电压的要求，对周围区域的良好隔离以及硅片上的最小表面。 这是通过具有用于高于100V的高额定电压的漏极（30）和源极（28）的细长MOS功率晶体管实现的，其中晶体管包括在边缘区域中的隔离沟槽（22），用于防止在额定电压之下的早期电气突破 。 沟槽衬有隔离材料（70,72），其中隔离沟槽终止电路部件。

公开(公告)号：US08793116B2

公开(公告)日：2014-07-29

申请号：US13474846

申请日：2012-05-18

申请人： Ralf Lerner ,  Wolfgang Miesch

发明人： Ralf Lerner ,  Wolfgang Miesch

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

摘要： A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

摘要翻译： 一种用于设计具有指定设计功率电平的第一垂直MOS功率晶体管的方法。 该方法包括以下步骤：将垂直MOS功率晶体管的布局组合成至少部分不同的布局部分，每个部分具有已知的设计数据，部分包括至少一个第一布局部分，其包括 给定数量的单晶体管单元，并且通过使用部件的已知设计数据并且基于部件的布局组合来调整第一垂直MOS功率晶体管的指定设计功率电平。

公开(公告)号：US08546207B2

公开(公告)日：2013-10-01

申请号：US13505101

申请日：2010-11-02

申请人： Gabriel Kittler ,  Ralf Lerner

发明人： Gabriel Kittler ,  Ralf Lerner

IPC分类号： H01L21/338

CPC分类号： H01L21/8258 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1203

摘要： The invention describes a method for fabricating silicon semiconductor wafers with the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafers are used, the active semiconductor layer of which has the III-V semiconductor layers (24) of the HEMT design (2) placed on it stretching over two mutually insulated regions (24a, 24b) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.

摘要翻译： 本发明描述了一种用于制造具有来自III-V半导体层的层结构的硅半导体晶片的方法，用于基于具有硅组件的半导体III-V层的HEMT的集成。 使用SOI硅半导体晶片，其有源半导体层具有放置在其上的HEMT设计（2）的III-V半导体层（24），其在有源硅层的两个相互绝缘的区域（24a，24b）上延伸。 同样公开了适当的层布置。

公开(公告)号：US20120306010A1

公开(公告)日：2012-12-06

申请号：US13579155

申请日：2010-02-15

申请人： Ralf Lerner ,  Phil Hower ,  Gabriel Kittler ,  Klaus Schottmann

发明人： Ralf Lerner ,  Phil Hower ,  Gabriel Kittler ,  Klaus Schottmann

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7828 ,  H01L29/0623 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66666

摘要： A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.

摘要翻译： 耗尽型DMOS晶体管包括电极材料中的间隙，允许将阱掺杂剂物质并入到下面的半导体材料中。 在随后的掺杂剂扩散期间，获得具有延伸的横向延伸而不增加深度的连续阱区。 掩蔽间隙后植入源掺杂剂物质。 在形成栅极电介质材料之前执行附加沟道注入。