公开(公告)号：US20240394346A1

公开(公告)日：2024-11-28

申请号：US18201675

申请日：2023-05-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ahmet Artu Yildirim

IPC: G06F21/10 ,  G06F21/62

Abstract: A distributed processing system includes one or more accelerated units (AUs) connected to a network. To control access to the AUs by one or more users over the network, the distributed processing system includes a control plane circuitry connected to the network. The control plane circuitry is configured to grant a user access to one or more AUs connected to the network based on user security data stored at the control plane circuitry. The security data stored at the control plane circuitry indicates which resources of one or more AUs connected to the network one or more users are authorized to access.

公开(公告)号：US12154224B2

公开(公告)日：2024-11-26

申请号：US17033023

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jan H. Achrenius ,  Kiia Kallio ,  Miikka Kangasluoma ,  Ruijin Wu ,  Anirudh R. Acharya

IPC: G06T17/10 ,  G06T1/20 ,  G06T15/00

Abstract: Some implementations provide systems, devices, and methods for rendering a plurality of primitives of a frame, the plurality of primitives being divided into a plurality of batches of primitives and the frame being divided into a plurality of bins. For at least one batch of the plurality of batches the rendering includes, for each of the plurality of bins, rendering primitives of a first sub-batch rasterizing to that bin, and for each of the plurality of bins, rendering primitives of a second sub-batch rasterizing to that bin.

公开(公告)号：US12153927B2

公开(公告)日：2024-11-26

申请号：US16889010

申请日：2020-06-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur ,  Marius Evers ,  Aparna Mandke ,  Steven R. Havlir ,  Robert Cohen ,  Anthony Jarvis

IPC: G06F9/38 ,  G06F9/48

Abstract: Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

公开(公告)号：US12153926B2

公开(公告)日：2024-11-26

申请号：US18393657

申请日：2023-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Michael T. Clark ,  Marius Evers ,  William L. Walker ,  Paul Moyer ,  Jay Fleischman ,  Jagadish B. Kotra

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US12153922B2

公开(公告)日：2024-11-26

申请号：US18147075

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew R Poremba ,  Ersin Cukurtas

IPC: G06F9/30 ,  G06F7/02

Abstract: In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing subsequent computations based on an output of the PIM component matching the programmed check value.

公开(公告)号：US20240385872A1

公开(公告)日：2024-11-21

申请号：US18198981

申请日：2023-05-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Martha Massee Barker ,  Anthony Thomas Gutierrez ,  Mark Unruh Wyse ,  Ali Arda Eker

IPC: G06F9/48

Abstract: In accordance with the described techniques for aggregation and scheduling of accelerator executable tasks, an accelerator device includes a processing element array and a command processor to receive a plurality of fibers each including multiple tasks and dependencies between the multiple tasks. The command processor places a first fiber in a sleep pool based on a first task within the first fiber having an unresolved dependency, and the command processor further places a second fiber in a ready pool based on a second task within the second fiber having a resolved dependency. Based on the second fiber being in the ready pool, the command processor launches the second task to be executed by the processing element array.

公开(公告)号：US20240370077A1

公开(公告)日：2024-11-07

申请号：US18312522

申请日：2023-05-04

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Paul A. Mackey ,  Michael John Austin ,  Xinzhe Li ,  Alexander S. Duenas ,  Davis Matthew Castillo ,  Ashwini Chandrashekhara Holla

IPC: G06F1/3296

Abstract: A computing device is provided which comprises memory and a processor in communication with the memory. The processor is configured to autonomously acquire input parameter values, comprising one of monitored device input parameter values from a component of the computing device and monitored user input parameter values. The processor is also configured to select, from a plurality of modes of operation, a mode of operation comprising parameter settings which are determined based on the acquired input parameter values, each of the plurality of modes of operation comprising different parameter settings configured to control the computing device to operate at a different level of performance. The processor is also configured to control operation of the computing device by tuning the parameter settings of the computing device according to the selected mode of operation comprising the determined parameter settings.

公开(公告)号：US12131026B2

公开(公告)日：2024-10-29

申请号：US18090916

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Nuwan S Jayasena ,  Niti Madan

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request stall threshold and a non-processing-in-memory request stall threshold. In response to a system switching (e.g., from executing processing-in-memory requests to executing non-processing-in-memory requests or from executing non-processing-in-memory requests to executing processing-in-memory requests), the memory controller modifies the processing-in-memory request stall threshold and the non-processing-in-memory request stall threshold. The memory controller continues scheduling an order of execution for subsequent requests received from the host using the modified stall thresholds.

公开(公告)号：US12120364B2

公开(公告)日：2024-10-15

申请号：US18094161

申请日：2023-01-06

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lei Zhang ,  Gabor Sines ,  Khaled Mammou ,  David Glen ,  Layla A. Mah ,  Rajabali M. Koduri ,  Bruce Montag

IPC: G06F15/16 ,  H04L65/70 ,  H04L65/75 ,  H04L67/131 ,  H04L69/24 ,  H04N21/2343 ,  H04N21/236 ,  H04N21/2368 ,  H04N21/414 ,  H04N21/422 ,  H04N21/43 ,  H04N21/434 ,  H04N21/437

CPC classification number: H04N21/2343 ,  H04L65/70 ,  H04L65/762 ,  H04L67/131 ,  H04L69/24 ,  H04N21/23605 ,  H04N21/2368 ,  H04N21/41407 ,  H04N21/42202 ,  H04N21/43072 ,  H04N21/4341 ,  H04N21/4343 ,  H04N21/437

Abstract: A device and method for processing Virtual Reality (VR) data is disclosed. The method comprises transmitting feedback information from the device to a server, wherein the feedback information is captured in the device, receiving data from the server to be presented on the device based on the feedback information, wherein the data includes video data and audio data where the video data is a frame of video data in a sequence of frames and the audio data is the corresponding audio data of the frame, decoding the video data and corresponding audio data of the frame, and controlling the presentation of the video data and corresponding audio data on the device such that the video data is synchronized with the corresponding audio data.

公开(公告)号：US12118656B2

公开(公告)日：2024-10-15

申请号：US18304115

申请日：2023-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/52

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.