公开(公告)号：US20100330753A1

公开(公告)日：2010-12-30

申请号：US12879401

申请日：2010-09-10

Applicant: Pil-Kyu Kang ,  Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Byeong-Chan Lee ,  InSoo Jung

Inventor： Pil-Kyu Kang ,  Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Byeong-Chan Lee ,  InSoo Jung

IPC: H01L21/336 ,  C30B1/02

CPC classification number: H01L21/823425 ,  H01L21/823475

Abstract: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.

Abstract translation: 在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。 绝缘层图案在其中具有部分地暴露第一单晶层的开口。 种子层在开口处。 第二单晶层位于绝缘层图案和籽晶层上。 第二单晶层具有与种子层基本相同的晶体结构。 转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。 转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

公开(公告)号：US20100240197A1

公开(公告)日：2010-09-23

申请号：US12793809

申请日：2010-06-04

Applicant: Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

Inventor： Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

IPC: H01L21/20

CPC classification number: H01L21/823418 ,  H01L21/823456 ,  H01L27/105 ,  H01L27/1052

Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.

Abstract translation: 本发明的实施例提供一种半导体集成电路器件及其制造方法。 半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由 隔离区。 半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层 所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

公开(公告)号：US07494877B2

公开(公告)日：2009-02-24

申请号：US11691529

申请日：2007-03-27

Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

IPC: H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/66795

Abstract: A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.

Abstract translation: 形成半导体器件的方法可以包括形成从衬底延伸的翅片结构。 翅片结构可以包括第一和第二源极/漏极区域和它们之间的沟道区域，并且第一和第二源极/漏极区域可以比沟道区域延伸比衬底更大的距离。 可以在沟道区上形成栅极绝缘层，并且可以在栅极绝缘层上形成栅电极，使得栅极绝缘层位于栅电极和沟道区之间。 还讨论了相关设备。

公开(公告)号：US20080073730A1

公开(公告)日：2008-03-27

申请号：US11902404

申请日：2007-09-21

Applicant: Deok-Hyung Lee ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Byeong-Chan Lee ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Byeong-Chan Lee ,  In-Soo Jung

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method for forming a semiconductor device includes forming at least one gate electrode having a bent structure along a first direction on a semiconductor substrate, the gate electrode having first and second vertical portions, forming at least one semiconductor fin along a second direction on the semiconductor substrate, the semiconductor fin positioned between the first and second vertical portions of the gate electrode, forming a first epitaxial layer on the semiconductor fin, the first epitaxial layer including a source/drain impurity region, and forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a contact impurity region.

Abstract translation: 一种形成半导体器件的方法包括：在半导体衬底上沿着第一方向形成具有弯曲结构的至少一个栅电极，所述栅极具有第一和第二垂直部分，在半导体上沿着第二方向形成至少一个半导体鳍片 衬底，所述半导体鳍片位于所述栅电极的所述第一和第二垂直部分之间，在所述半导体鳍片上形成第一外延层，所述第一外延层包括源/漏杂质区，以及在所述第一外延层上形成第二外延层 层，第二外延层包括接触杂质区。

公开(公告)号：US20070190732A1

公开(公告)日：2007-08-16

申请号：US11691529

申请日：2007-03-27

Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/66795

Abstract: A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.

Abstract translation: 形成半导体器件的方法可以包括形成从衬底延伸的翅片结构。 翅片结构可以包括第一和第二源极/漏极区域和它们之间的沟道区域，并且第一和第二源极/漏极区域可以比沟道区域延伸比衬底更大的距离。 可以在沟道区上形成栅极绝缘层，并且可以在栅极绝缘层上形成栅电极，使得栅极绝缘层位于栅电极和沟道区之间。 还讨论了相关设备。

公开(公告)号：US07205609B2

公开(公告)日：2007-04-17

申请号：US10853616

申请日：2004-05-25

Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/66795

Abstract: A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.

Abstract translation: 形成半导体器件的方法可以包括形成从衬底延伸的翅片结构。 翅片结构可以包括第一和第二源极/漏极区域和它们之间的沟道区域，并且第一和第二源极/漏极区域可以比沟道区域延伸比衬底更大的距离。 可以在沟道区上形成栅极绝缘层，并且可以在栅极绝缘层上形成栅电极，使得栅极绝缘层位于栅电极和沟道区之间。 还讨论了相关设备。

公开(公告)号：US20070004107A1

公开(公告)日：2007-01-04

申请号：US11530651

申请日：2006-09-11

Applicant: Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66803

Abstract: Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described

Abstract translation: 集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。 沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。 源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。 还描述了相关的制造方法

公开(公告)号：US20060202270A1

公开(公告)日：2006-09-14

申请号：US11433942

申请日：2006-05-15

Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

Abstract: A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

Abstract translation: 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。

公开(公告)号：US06900102B2

公开(公告)日：2005-05-31

申请号：US10773022

申请日：2004-02-05

Applicant: Byeong-Chan Lee ,  Si-Young Choi ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  In-Soo Jung

Inventor： Byeong-Chan Lee ,  Si-Young Choi ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  In-Soo Jung

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/786

CPC classification number: H01L29/78648 ,  H01L21/823437 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/78645

Abstract: A double gate electrode for a field effect transistor is fabricated by forming in a substrate, a trench and a tunnel that extends from a sidewall of the trench parallel to the substrate. An insulating coating is formed inside the tunnel. A bottom gate electrode is formed within the insulating coating inside the tunnel. An insulating layer is formed on the substrate and a top gate electrode is formed on the insulating layer opposite the bottom gate electrode.

Abstract translation: 用于场效应晶体管的双栅极通过在衬底，沟槽和从沟槽的侧壁平行于衬底延伸的隧道中形成来制造。 在隧道内形成绝缘涂层。 底部栅电极形成在隧道内部的绝缘涂层内。 在衬底上形成绝缘层，并且在与栅电极相对的绝缘层上形成顶栅电极。

公开(公告)号：US20050104096A1

公开(公告)日：2005-05-19

申请号：US10937246

申请日：2004-09-09

Applicant: Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

Inventor： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

IPC: H01L21/28 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/332 ,  H01L21/8234 ,  H01L29/76 ,  H01L31/062

CPC classification number: H01L29/785 ,  H01L21/823842 ,  H01L29/42384 ,  H01L29/66795

Abstract: A fin field effect transistor (FinFET) includes a first gate and a second gate. The first gate has a vertical part that is defined by sidewalls of a silicon fin and sidewalls of a capping pattern disposed on the silicon fin and a horizontal part horizontally extends from the vertical part. The second gate is made of a low-resistivity material and is in direct contact with the horizontal part of the first gate. A channel may be controlled due to the first gate, and a device operating speed may be enhanced due to the second gate. Related fabrication methods also are described.

Abstract translation: 鳍状场效应晶体管（FinFET）包括第一栅极和第二栅极。 第一栅极具有由硅翅片的侧壁和设置在硅片上的封盖图案的侧壁限定的垂直部分，并且水平部分从垂直部分水平延伸。 第二栅极由低电阻率材料制成，并与第一栅极的水平部分直接接触。 由于第一门可以控制通道，并且由于第二门可能会增强设备运行速度。 还描述了相关的制造方法。