公开(公告)号：US20080188042A1

公开(公告)日：2008-08-07

申请号：US11777769

申请日：2007-07-13

Applicant: Byeong-Jin LEE ,  Sang-Gab KIM ,  Hong-Sick PARK

Inventor： Byeong-Jin LEE ,  Sang-Gab KIM ,  Hong-Sick PARK

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

Abstract: Provided is a method of manufacturing a thin film transistor panel that may reduce manufacturing costs. The method includes forming gate wires including a gate line and a gate electrode on an insulating substrate and forming data wires including source and drain electrodes, the data wires being insulated from the gate wires. The method further includes forming a passivation layer covering the gate and data wires, forming contact holes exposing the drain electrodes by etching the passivation layer, and forming a pixel electrode by depositing an indium-free transparent conductive film on the exposed drain electrode and the passivation layer and then dry etching the transparent conductive film.

Abstract translation: 提供了可以降低制造成本的薄膜晶体管面板的制造方法。 该方法包括在绝缘衬底上形成包括栅极线和栅电极的栅极线，并形成包括源极和漏极的数据线，数据线与栅极线绝缘。 该方法还包括形成覆盖栅极和数据线的钝化层，形成通过蚀刻钝化层而暴露出漏电极的接触孔，以及通过在暴露的漏电极和钝化层上沉积无铟透明导电膜来形成像素电极 然后干燥蚀刻透明导电膜。

公开(公告)号：US20080169471A1

公开(公告)日：2008-07-17

申请号：US12008156

申请日：2008-01-08

Applicant: Won-Suk Shin ,  Hong-Sick Park ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Byeong-Jin Lee

Inventor： Won-Suk Shin ,  Hong-Sick Park ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Byeong-Jin Lee

IPC: H01L29/04 ,  H01L21/84

CPC classification number: G02F1/13458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

Abstract: A display substrate includes a gate line, a data line, a pixel electrode and a source pad part. The gate line is formed on a base substrate. The data line crosses the gate line to define a pixel area. The pixel electrode makes contact with the base substrate. The source pad part is formed on an end portion of the data line, the source pad part including a source metal layer, a conductive etch stop layer formed on the source metal layer and a source pad electrode formed on the conductive etch stop layer. Thus, the conductive etch stop layer of the source pad part prevents the source metal layer of the source pad part from being damaged and the conductive etch stop layer of the source pad part may fully make contact with the source pad electrode.

Abstract translation: 显示基板包括栅极线，数据线，像素电极和源极焊盘部分。 栅极线形成在基底基板上。 数据线与栅极线交叉以定义像素区域。 像素电极与基底基板接触。 源极焊盘部分形成在数据线的端部，源焊盘部分包括源极金属层，形成在源极金属层上的导电蚀刻停止层和形成在导电蚀刻停止层上的源极焊盘电极。 因此，源极焊盘部分的导电蚀刻停止层防止源极焊盘部分的源极金属层被损坏，并且源极焊盘部分的导电蚀刻停止层可以完全与源极焊盘电极接触。

公开(公告)号：US20080164471A1

公开(公告)日：2008-07-10

申请号：US11985199

申请日：2007-11-13

Applicant: Jong-hyun Choung ,  Byeong-Jin Lee ,  Hong-sick Park ,  Sun-young Hong ,  Bong-kyun Kim ,  Won-suk Shin

Inventor： Jong-hyun Choung ,  Byeong-Jin Lee ,  Hong-sick Park ,  Sun-young Hong ,  Bong-kyun Kim ,  Won-suk Shin

IPC: H01L27/12 ,  H01L21/70

CPC classification number: H01L27/1288 ,  G02F1/136227 ,  H01L27/1214

Abstract: A thin film transistor substrate that has reduced production cost and defect rate is presented. The thin film transistor substrate includes a gate wiring line formed on an insulating substrate and including a gate electrode, a data wiring line formed on the gate wiring line and including a source electrode and a drain electrode, a passivation layer pattern formed on parts of the data wiring line other than the drain electrode and a pixel region, and a pixel electrode electrically connected to the drain electrode. The pixel electrode includes zinc oxide.

Abstract translation: 介绍了降低生产成本和缺陷率的薄膜晶体管基板。 薄膜晶体管基板包括形成在绝缘基板上并包括栅电极的栅极布线，形成在栅极布线上并包括源电极和漏电极的数据布线，形成在栅极布线的一部分上的钝化层图案 除了漏电极和像素区域之外的数据布线，以及与漏电极电连接的像素电极。 像素电极包括氧化锌。

公开(公告)号：US20080067603A1

公开(公告)日：2008-03-20

申请号：US11696097

申请日：2007-04-03

Applicant: Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Yoon ,  Jeong-Min Park ,  Doo-Hee Jung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

Inventor： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Yoon ,  Jeong-Min Park ,  Doo-Hee Jung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC: H01L21/00 ,  H01L29/76

CPC classification number: H01L27/1288 ,  H01L27/1214

Abstract: A method of manufacturing a thin film transistor array panel, including: forming gate lines on a substrate; forming a gate insulating layer on the gate lines; forming semiconductor layers on the gate insulating layer; forming data lines and drain electrodes on the semiconductor layers; depositing a passivation layer on the data lines and the drain electrodes; forming a first photoresist layer including a first portion and a second portion that is thinner than the first portion on the passivation layer; forming a first preliminary contact hole exposing the data lines by etching the passivation layer by using the first photoresist layer as a mask; removing the second portion of the first photoresist; forming a first contact hole by expanding the first preliminary contact hole and opening portions by etching the passivation layer by using the first portion of the first photoresist layer as a mask; depositing a conductor layer; and forming pixel electrodes in the opening portions and a first contact assistant member in the first contact hole by removing the first photoresist layer and the conductor layer located thereon.

Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括：在衬底上形成栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在半导体层上形成数据线和漏电极; 在数据线和漏电极上沉积钝化层; 形成第一光致抗蚀剂层，其包括比钝化层上的第一部分更薄的第一部分和第二部分; 通过使用第一光致抗蚀剂层作为掩模，形成通过蚀刻钝化层而暴露数据线的第一预接触孔; 去除第一光致抗蚀剂的第二部分; 通过使用第一光致抗蚀剂层的第一部分作为掩模，通过蚀刻钝化层来扩展第一预接触孔和开口部来形成第一接触孔; 沉积导体层; 以及通过去除位于其上的第一光致抗蚀剂层和导体层，在开口部分中形成像素电极和第一接触孔中的第一接触辅助部件。

公开(公告)号：US08755019B2

公开(公告)日：2014-06-17

申请号：US13193488

申请日：2011-07-28

Applicant: Ji-Young Park ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

Inventor： Ji-Young Park ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

IPC: G02F1/1339 ,  G02F1/13

CPC classification number: H01L27/1288 ,  G02F1/1362 ,  G02F2001/136231 ,  H01L29/41733

Abstract: A method of manufacturing a liquid crystal display includes: forming a gate line including a gate electrode on a first substrate; forming a gate insulating layer on the gate line; sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer; aligning the edges of the semiconductor layer and the data metal layer; forming a transparent conductive layer on the gate insulating layer and the data metal layer; forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer; and forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode.

Abstract translation: 制造液晶显示器的方法包括：在第一基板上形成包括栅电极的栅极线; 在栅极线上形成栅极绝缘层; 在栅极绝缘层的整个表面上依次形成半导体层，非晶硅层和数据金属层; 对准半导体层和数据金属层的边缘; 在栅绝缘层和数据金属层上形成透明导电层; 通过图案化透明导电层形成第一像素电极和第二像素电极; 以及使用所述第一像素电极和所述第二像素电极作为掩模，通过蚀刻所述数据金属层和所述非晶硅层来形成包括源电极，漏电极和欧姆接触层的数据线，并且使所述半导体在 源电极和漏电极。

公开(公告)号：US20120295380A1

公开(公告)日：2012-11-22

申请号：US13566239

申请日：2012-08-03

Applicant: Bong-Kyun Kim ,  Jong-Hyun Choung ,  Byeong-Jin Lee ,  Sun-Young Hong ,  Hong-Sick Park ,  Shi-Yul Kim ,  Ki-Beom Lee ,  Sam-Young Cho ,  Sang-Woo Kim ,  Hyun-Cheol Shin ,  Won-Guk Seo

Inventor： Bong-Kyun Kim ,  Jong-Hyun Choung ,  Byeong-Jin Lee ,  Sun-Young Hong ,  Hong-Sick Park ,  Shi-Yul Kim ,  Ki-Beom Lee ,  Sam-Young Cho ,  Sang-Woo Kim ,  Hyun-Cheol Shin ,  Won-Guk Seo

IPC: H01L33/08

CPC classification number: C23F1/26 ,  C23F1/18 ,  H01L21/32134 ,  H01L27/124 ,  H01L29/458

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract translation: 蚀刻剂包括约0.1重量％至约30重量％的过硫酸铵（NH 4）2 S 2 O 8，约0.1重量％至约10重量％的无机酸，约0.1重量％至约10重量％的 约0.01重量％至约5重量％的含氟化合物的乙酸盐，约0.01重量％至约5重量％的磺酸化合物，约0.01重量％至约2重量％ 的唑类化合物，剩余的水。 因此，蚀刻剂可能具有高稳定性以保持蚀刻能力。 因此，可以提高制造裕度，从而可以降低制造成本。

公开(公告)号：US08044398B2

公开(公告)日：2011-10-25

申请号：US12331138

申请日：2008-12-09

Applicant: Hong-Long Ning ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Hong-Sick Park ,  Joo-Ae Youn ,  Byeong-Beom Kim ,  Byeong-Jin Lee

Inventor： Hong-Long Ning ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Hong-Sick Park ,  Joo-Ae Youn ,  Byeong-Beom Kim ,  Byeong-Jin Lee

IPC: H01L29/04 ,  H01L29/15 ,  H01L27/01 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

Abstract: A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.

Abstract translation: 显示基板包括绝缘基板，薄膜晶体管（TFT），像素电极，信号线和焊盘部分。 绝缘基板具有显示区域和围绕显示区域的周边区域。 TFT位于绝缘基板的显示区域。 像素电极在绝缘基板的显示区域中并与TFT电连接。 信号线位于绝缘基板上，并从周边区域向显示区域延伸。 焊盘部分在外围区域中并且电连接到信号线。 衬垫部分形成在绝缘衬底的沟槽中，并且包括延伸到绝缘衬底中的区域。 因此，信号线可以牢固地附接到绝缘基板。

公开(公告)号：US20110256712A1

公开(公告)日：2011-10-20

申请号：US12857959

申请日：2010-08-17

Applicant: Byeong-Jin LEE ,  Hong-Sick PARK ,  Tai-Hyung RHEE ,  Yong-Sung SONG ,  Choung-Woo PARK ,  Jong-Hyun OH

Inventor： Byeong-Jin LEE ,  Hong-Sick PARK ,  Tai-Hyung RHEE ,  Yong-Sung SONG ,  Choung-Woo PARK ,  Jong-Hyun OH

IPC: H01L21/768 ,  C09K13/08 ,  C09K13/10 ,  C09K13/00

CPC classification number: C09K13/10 ,  C23F1/10 ,  C23F1/44 ,  H01L21/32134 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/4908

Abstract: The present invention relates to an etchant for etching metal wiring, and the metal wiring etchant according to the present invention includes hydrogen peroxide at about 5 wt % to about 15 wt %, an oxidant at about 0.5 wt % to about 5 wt %, a fluoride-based compound at about 0.1 wt % to about 1 wt %, a nitrate-based compound at about 0.5 wt % to about 5 wt %, and a boron-based compound at about 0.05 wt % to about 1 wt %.

Abstract translation: 本发明涉及用于蚀刻金属布线的蚀刻剂，根据本发明的金属布线蚀刻剂包括约5重量％至约15重量％的过氧化氢，约0.5重量％至约5重量％的氧化剂， 约0.1重量％至约1重量％的氟化物基化合物，约0.5重量％至约5重量％的硝酸盐基化合物和约0.05重量％至约1重量％的硼基化合物。

公开(公告)号：US20110151631A1

公开(公告)日：2011-06-23

申请号：US13018309

申请日：2011-01-31

Applicant: Jong Hyun CHOUNG ,  Hong Sick PARK ,  Sun Young HONG ,  Bong Kyun KIM ,  Bong Kyu SHIN ,  Won Suk SHIN ,  Byeong Jin LEE

Inventor： Jong Hyun CHOUNG ,  Hong Sick PARK ,  Sun Young HONG ,  Bong Kyun KIM ,  Bong Kyu SHIN ,  Won Suk SHIN ,  Byeong Jin LEE

IPC: H01L21/336

CPC classification number: H01L27/1288 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate and a method of manufacturing the thin film transistor substrate comprises forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a stepped-structure occurring pattern overlapping at least one of the gate line and the data line; forming a passivation layer having a stepped-structure portion formed by the stepped-structure occurring pattern on the substrate; forming a photoresist pattern having a second stepped-structure portion corresponding to the stepped-structure portion on the passivation layer; patterning the passivation layer using the photoresist pattern as a mask; forming a transparent conductive layer on the substrate; and removing the photoresist pattern where the transparent conductive layer is covered by a stripper penetrating through the stepped-structure portion of the photoresist pattern and forming a pixel electrode connected to the thin film transistor.

Abstract translation: 薄膜晶体管基板和薄膜晶体管基板的制造方法包括形成栅极线和数据线，该栅极线和数据线被插入并且限定基板上的像素区域的栅极绝缘层彼此相交，薄膜晶体管电连接到 栅极线和数据线，以及与栅极线和数据线中的至少一个重叠的阶梯结构发生图案; 在所述基板上形成具有由阶梯状结构发生图案形成的台阶状部分的钝化层; 形成具有对应于所述钝化层上的阶梯状结构部分的第二阶梯结构部分的光致抗蚀剂图案; 使用光致抗蚀剂图案作为掩模来图案化钝化层; 在所述基板上形成透明导电层; 以及去除透明导电层被穿透光致抗蚀剂图案的台阶结构部分的剥离剂覆盖的光致抗蚀剂图案，并形成连接到薄膜晶体管的像素电极。

公开(公告)号：US20110014737A1

公开(公告)日：2011-01-20

申请号：US12890324

申请日：2010-09-24

Applicant: Jong-Hyun CHOUNG ,  Hong-Sick Park ,  Joo-Ae Youn ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

Inventor： Jong-Hyun CHOUNG ,  Hong-Sick Park ,  Joo-Ae Youn ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC: H01L21/8234

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/4908

Abstract: A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

Abstract translation: 薄膜晶体管阵列及其制造方法包括由基板上的透明导电层形成的像素电极，由透明导电层形成的栅极线和基板上的不透明导电层，连接到栅极的栅电极 并且在基板上形成透明导电层和不透明导电层，覆盖栅极线和栅极的栅极绝缘层，形成在栅极绝缘层上以与栅电极重叠的半导体层，数据线， 与栅极线相交，连接到数据线的源电极与半导体层的一部分重叠，以及连接到像素电极以与半导体层的一部分重叠的漏电极。