公开(公告)号：US07272677B1

公开(公告)日：2007-09-18

申请号：US10637982

申请日：2003-08-08

申请人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

IPC分类号： G06F3/00 ,  G06F13/12

CPC分类号： H03K19/1774 ,  G06F1/12 ,  H03K19/17744 ,  H03K19/17792

摘要： A serial interface for a programmable logic device substantially eliminates skew across multiple channels both in the receiver and in the transmitter. Even when the channels are independent (e.g., are in different quads), skew is substantially eliminated by monitoring to determine when all channels have reached their active states (i.e., in the case of receiver channels when all channels have achieved byte alignment and have received an alignment character, and in the case of transmitter channels when all transmit PLLs have locked), and only then allowing data to flow between the serial and parallel domains.

摘要翻译： 用于可编程逻辑器件的串行接口基本上消除了接收器和发射器中的多个通道的偏移。 即使当信道是独立的（例如，处于不同的四边形）时，通过监视基本上消除了偏差，以便确定所有信道何时已经达到其活动状态（即，在所有信道已经实现字节对齐并已经接收到的信道的情况下 对齐字符，并且在所有发送PLL锁定时在发送器通道的情况下），并且仅允许数据在串行和并行域之间流动。

公开(公告)号：US07180972B1

公开(公告)日：2007-02-20

申请号：US10273899

申请日：2002-10-16

申请人： Ramanand Venkata ,  Chong H Lee

发明人： Ramanand Venkata ,  Chong H Lee

IPC分类号： H04L7/00

CPC分类号： G06F1/10

摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.

摘要翻译： 可编程逻辑器件（“PLD”）包括高速串行接口（“HSSI”）电路。 HSSI电路包括时钟信号电路，其允许HSSI电路的各种组件以不同的方式计时，以便于使用HSSI电路来支持多种不同的通信协议。 一些HSSI时钟信号可以通过相关联的PLD逻辑电路的时钟分配网络路由。 HSSI电路可以包括相位补偿缓冲器电路，以补偿跨越HSSI电路和相关联的PLD逻辑电路之间的接口上的可能的相位差。

公开(公告)号：US07151397B2

公开(公告)日：2006-12-19

申请号：US10873578

申请日：2004-06-22

申请人： Stjepan W Andrasic ,  Rakesh H Patel ,  Chong H Lee

发明人： Stjepan W Andrasic ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： H03H11/26 ,  H03B5/24

CPC分类号： H03K5/133 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/0995 ,  H03L7/10

摘要： A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

公开(公告)号：US07131024B1

公开(公告)日：2006-10-31

申请号：US10670813

申请日：2003-09-24

申请人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

IPC分类号： G06F1/06

CPC分类号： G06F1/06

摘要： A serial interface for a programmable logic device provides multiple data rates in different channels by generating a central serial clock and providing at least one divider in each channel that can divide the central clock by different integer values. For additional variation in clock rate, two or more different central clocks can be provided, with each channel then being able to divide any of the central clocks to provide the desired local clock. Lower speed parallel clocks can be generated locally by further dividing the divided serial clock. Alternatively, the central serial clock or clocks may be divided centrally to provide a central parallel clock or clocks which can then be used locally as a local parallel clock.

摘要翻译： 用于可编程逻辑器件的串行接口通过产生中央串行时钟来在不同的通道中提供多个数据速率，并且在每个通道中提供至少一个可以将中心时钟除以不同整数值的分频器。 对于时钟速率的额外变化，可以提供两个或多个不同的中央时钟，每个信道然后能够分割任何中央时钟以提供期望的本地时钟。 可以通过进一步分割串行时钟来本地生成低速并行时钟。 或者，中央串行时钟可以集中分配以提供中央并行时钟或时钟，然后可以将其本地地用作本地并行时钟。

公开(公告)号：US07088133B2

公开(公告)日：2006-08-08

申请号：US11302722

申请日：2005-12-13

申请人： Chong H Lee ,  Reza Asayesh

发明人： Chong H Lee ,  Reza Asayesh

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17732

摘要： A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FiberChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

摘要翻译： 可编程逻辑器件（“PLD”）包括可支持若干高速串行（“HSS”）标准的高速串行接口（“HSSI”）电路。 可以支持的标准的例子有XAUI，InfiniBand，1G以太网，FiberChannel和Serial RapidIO。 HSSI电路可以部分地可编程以支持这些各种标准。 在某些情况下，控制可能来自相关的PLD核心电路。 同样在某些情况下，一些接口功能可以在PLD核心电路中执行。

公开(公告)号：US07002368B2

公开(公告)日：2006-02-21

申请号：US11128916

申请日：2005-05-12

申请人： Chong H. Lee ,  Reza Asayesh

发明人： Chong H. Lee ,  Reza Asayesh

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/17732

摘要： A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

公开(公告)号：US06943588B1

公开(公告)日：2005-09-13

申请号：US10670146

申请日：2003-09-24

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US06911841B2

公开(公告)日：2005-06-28

申请号：US10643276

申请日：2003-08-18

申请人： Chong H. Lee ,  Reza Asayesh

发明人： Chong H. Lee ,  Reza Asayesh

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17732

摘要： A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

公开(公告)号：US09049120B1

公开(公告)日：2015-06-02

申请号：US13175740

申请日：2011-07-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04L27/00 ,  H04L12/24

CPC分类号： H04L41/0833 ,  H04L12/40013 ,  Y02B60/35

摘要： A method and system for operating a communication circuit during periods of reduced energy consumption are disclosed. Data may be transmitted over a communication link from a first device to a second device in a low-power state. The data may be used by the second device to update coefficients and/or synchronize the receiver of the second device to a transmitter of the first device, thereby enabling a more efficient or rapid transition from the low-power state to an active state. A transmitter of the first device and a receiver of the second device may be activated before transmission of the data and deactivated after transmission of the data. In this manner, a receiver of the second device may be refreshed to enable a more efficient transition from the low-power state to an active state.

摘要翻译： 公开了一种在降低能量消耗期间操作通信电路的方法和系统。 数据可以通过通信链路从低功率状态从第一设备传输到第二设备。 该数据可以被第二设备用来更新系统和/或将第二设备的接收机同步到第一设备的发射机，从而能够从低功率状态到活动状态的更有效或快速的转变。 第一设备的发射机和第二设备的接收机可以在传输数据之前激活，并且在传输数据之后停用。 以这种方式，可以刷新第二设备的接收机，以便能够从低功率状态到活动状态的更有效的转变。

公开(公告)号：US08787352B2

公开(公告)日：2014-07-22

申请号：US13103132

申请日：2011-05-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04L12/28 ,  H04L5/14 ,  H04L27/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。