公开(公告)号：US09361419B2

公开(公告)日：2016-06-07

申请号：US14453585

申请日：2014-08-06

Applicant: ESS Technology, Inc.

Inventor： Robert L. Blair ,  Daniel A. Risler ,  A Martin Mallinson

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207

Abstract: An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.

Abstract translation: 公开了一种用于放置和布线化学元件的改进方法，每个复合元件包括名义上相同的元件的串联/并联组合。 该方法将每个复合元素作为单独的单元（通常用于硅芯片设计的子电路构造）来处理，以便将作为单位的所有名义上相同的元素作为单元处理，并将它们作为单个组 芯片的设计。 这导致复合元素被放置为单元并以这样的方式布线，使得所有标称元素位于一起，并且化合物值之间的任何影响因此相对局部化并且被最佳隔离。

公开(公告)号：US20150222249A1

公开(公告)日：2015-08-06

申请号：US14619940

申请日：2015-02-11

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: H03H17/02 ,  H03M1/74 ,  H03M1/68

CPC classification number: H03H17/0248 ,  B60N2/002 ,  H03H15/00 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.

Abstract translation: 描述通道选择滤波器电路。 一个电路实现了一个乘法元件和数 - 模转换器作为差分电流模式器件。 实现乘法元件的另一个电路和具有加权相加的数模转换器，在数模转换器和乘法器组合的乘法之后延迟。 在一个这样的电路中，基本相等的电流源幅度在电路的不同列中。 另一个具有基本上相等的电流源幅度的这种电路使用非基数2。 具有基本相等的电流源幅度的另一个这样的电路具有部分分割。 另一电路实现了乘法元件和数模转换器，具有部分分段，元件的加扰位分配。 如这里所述，一个这样的电路对等加权的片段进行比特分配。 另一个电路实现了具有选择性地启用重复的电流源装置的乘法元件和数模转换器。 另一电路实现了具有可变有效长度的数模转换器的乘法元件和数 - 模转换器。 在一个这样的电路中，如本文所述，乘法器元件的一个或多个电流源被取消选择以去除乘法器元件的噪声贡献。 复合滤波器电路包括一对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享公共电阻网络以执行加权相加。 一个这样的电路还包括第二对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享第二公共电阻网络以执行加权相加。

公开(公告)号：US20150046894A1

公开(公告)日：2015-02-12

申请号：US14453585

申请日：2014-08-06

Applicant: ESS Technology, Inc.

Inventor： Robert L. Blair ,  Daniel A. Risler ,  A Martin Mallinson

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207

Abstract: An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.

Abstract translation: 公开了一种用于放置和布线化学元件的改进方法，每个复合元件包括名义上相同的元件的串联/并联组合。 该方法将每个复合元素作为单独的单元（通常用于硅芯片设计的子电路构造）来处理，以便将作为单位的所有名义上相同的元素作为单元处理，并将它们作为单个组 芯片的设计。 这导致复合元素被放置为单元并以这样的方式布线，使得所有标称元素位于一起，并且化合物值之间的任何影响因此相对局部化并且被最佳隔离。

公开(公告)号：US20150040085A1

公开(公告)日：2015-02-05

申请号：US14446780

申请日：2014-07-30

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5063 ,  G06F2217/02 ,  G06F2217/06

Abstract: A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve an arbitrary compound value is disclosed. A recursive algorithm successively adds one or more similar nominal two-terminal elements to generate a series and/or parallel compound combination of nominal elements, the compound combination having a desired impedance. The compound value, and thus the ratio between two compound values, can be determined to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the compound value, and the ratio between values, depends primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.

Abstract translation: 公开了一种用于产生和匹配名义上相同的初始元素以实现任意化合物值的复杂串联和/或并联组合的方法和系统。 递归算法连续地添加一个或多个相似的标称两端元件以产生具有期望阻抗的复合组合的标称元件的串联和/或并联复合组合。 可以将化合物值以及因此两个化合物值之间的比率确定为几乎任何所需的准确度，其中潜在误差比在不同值的各个元素的构造中典型地降低。 由于初始元素名义上相同，所以化合物值和值之间的比例主要取决于初始元素的连接而不是其几何形状，并且因此保持实质上恒定，而与制造过程中的变化无关。

公开(公告)号：US20140375356A1

公开(公告)日：2014-12-25

申请号：US14314882

申请日：2014-06-25

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K5/133 ,  H03K5/14 ,  H03K5/15046 ,  H03K19/00361 ,  H03K19/00369 ,  H03K19/018521

Abstract: A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode.

Abstract translation: 公开了一种延迟电路，其延迟与为延迟电路的逻辑门供电的电源的变化无关。 通过将偏置在受控电压的附加CMOS偏置晶体管分离形成每个逻辑门的CMOS晶体管，由于逆变器晶体管的电源电压的变化，反相晶体管的栅极延迟的变化可能被最小化。 在一个实施例中，恒定偏置电压可以由包括一系列放大器的恒定电流源提供，每个放大器的增益明显小于连接到三重共源共栅的一个。

公开(公告)号：US20140103977A1

公开(公告)日：2014-04-17

申请号：US14055772

申请日：2013-10-16

Applicant: ESS Technology, Inc.

Inventor： Hu Jing Yao ,  Dustin Dale Forman ,  A. Martin Mallinson

IPC: H03L7/195

CPC classification number: H03L7/195 ,  H03L7/18 ,  H03L7/235

Abstract: A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added, to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.

Abstract translation: 公开了一种方法和系统，其中锁相环中的相位检测器能够以适合于参考信号的最快速度运行。 将频偏添加到锁相环的输出频率，以改变馈送到分频器的频率，该分频器将常规PLL中的输出频率接收到中频。 选择频率偏移，使得中频与参考频率的比率是简单的分数，优选地是整数，即中频是参考频率的倍数。 在输出频率和参考频率之间的关系很大程度上相对于素数的情况下，相位检测器因此能够以参考信号的频率接收信号并且以适合于参考信号的最快速度进行操作。

公开(公告)号：US20040216007A1

公开(公告)日：2004-10-28

申请号：US10810312

申请日：2004-03-26

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson ,  Simon Jacques Damphousse

IPC: H02H003/05

CPC classification number: H03M3/344 ,  H03M3/358

Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract translation: 提供了一种系统和方法来补偿Σ-Δ电路中的输出误差。 该系统包括用于接收输入信号的输入端和被配置为输出输出信号的输出。 该系统还包括一个相加分量，其被配置为将从输出信号导出的第一误差电压值添加到输入输入信号，以及减法分量，被配置为减去第二误差电压值，其中第二误差电压值为 从输入输入信号中增加第一误差电压值得出。

公开(公告)号：US20040189390A1

公开(公告)日：2004-09-30

申请号：US10680811

申请日：2003-10-06

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03F003/45

CPC classification number: H03F3/45094 ,  H03F3/005 ,  H03F2203/45461

Abstract: A device is provided having at least two capacitive elements configured to retain a charge, and an interconnection of active devices between the capacitive elements. The active devices are configured to operate upon a transient charge flow as a current when in operation. The charge flow is partitioned into at least two capacitors according to the input voltage difference acting as a controlling parameter.

Abstract translation: 提供了一种器件，其具有被配置为保持电荷的至少两个电容元件以及在电容元件之间的有源器件的互连。 有源器件被配置为在瞬时充电流动时作为工作时的电流工作。 根据作为控制参数的输入电压差，将电荷流分成至少两个电容器。

公开(公告)号：US20030189508A1

公开(公告)日：2003-10-09

申请号：US10346034

申请日：2003-01-15

Applicant: ESS TECHNOLOGY, INC.

Inventor： Andrew Martin Mallinson

IPC: H03M001/36

CPC classification number: H03M1/367

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

公开(公告)号：US12224757B2

公开(公告)日：2025-02-11

申请号：US18117795

申请日：2023-03-06

Applicant: ESS Technology, Inc.

Inventor： Dustin Dale Forman ,  Libin Timothy George ,  Hassan Mohammadnavazi ,  Hu Jing Yao

IPC: H03L7/091 ,  H03L7/089 ,  H03L7/099

Abstract: A method and apparatus for reducing jitter in a phase-locked loop (PLL). Clock signals provided to the PLL are resampled into the voltage domain of the VCO in the PLL rather than being merely level shifted into that voltage domain or input directly from digital domain clock dividers as in the prior art. The resampling is done with flip-flops in the analog domain using a faster synchronous clock in each case, and results in cleaner clock edges being presented to the PLL than those provided by the digital circuitry alone. A divided input clock signal is resampled using the undivided input clock, while a divided feedback clock signal is resampled using the feedback clock signal itself, i.e., the output of the VCO in the PLL. This removes jitter caused by the processing of clock signals in the digital voltage domain and thus reduces the jitter in the output signal.