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    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS
    51.
    发明申请
    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS 失效
    包括选择的参考存储器单元的电阻存储器件

    公开(公告)号：US20090067216A1

    公开(公告)日：2009-03-12

    申请号：US12265941

    申请日：2008-11-06

    Applicant: Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    Inventor： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC: G11C11/00 ,  G11C11/02 ,  G11C7/00

    CPC classification number: G11C11/1675 ,  G11C11/1673

    Abstract: A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.

    Abstract translation: 磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流 源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流 耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线 与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为将第二偏置电压施加到未被选择以在读取期间访问的第一或第二存储器单元 操作。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE
    52.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE 有权
    具有过渡金属氧化物层的半导体器件的制造方法及相关器件

    公开(公告)号：US20090020745A1

    公开(公告)日：2009-01-22

    申请号：US12175602

    申请日：2008-07-18

    Applicant: Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh ,  Kyung-Tae Nam ,  In-Gyu Baek

    Inventor： Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh ,  Kyung-Tae Nam ,  In-Gyu Baek

    IPC: H01L21/329 ,  H01L47/00

    CPC classification number: H01L27/24 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/224

    Abstract: Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.

    Abstract translation: 提供一种具有能够防止蛇电流的开关装置的半导体器件的制造方法。 首先，将过渡金属氧化物层和泄漏控制层交替层叠在基板上1〜20次，以形成可变电阻层。 与其稳定状态相比，过渡金属氧化物层形成为含有过量的过渡金属。 泄漏控制层可以由选自Mg层，Ta层，Al层，Zr层，Hf层，多晶硅层，导电性碳基层和Nb层中的一种形成。

    Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated
    55.
    发明授权
    Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated 有权
    编程非易失性存储器件的方法包括作为数据存储材料层的过渡金属氧化物层和如此操作的器件

    公开(公告)号：US07292469B2

    公开(公告)日：2007-11-06

    申请号：US11282136

    申请日：2005-11-18

    Applicant: Moon-Sook Lee ,  In-Gyu Baek

    Inventor： Moon-Sook Lee ,  In-Gyu Baek

    IPC: G11C11/00

    CPC classification number: G11C13/00 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

    Abstract: A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to reduce a resistance of the transition metal oxide layer and applying a second electric pulse to the transition metal oxide layer for a second period, longer than the first period, to increase the resistance of the transition metal oxide layer. Related devices are also disclosed.

    Abstract translation: 一种对包括过渡金属氧化物层的非易失性存储器件进行编程的方法包括将第一电脉冲施加到过渡金属氧化物层第一周期以减小过渡金属氧化物层的电阻并向第二电脉冲施加第二电脉冲 过渡金属氧化物层，延长第一周期，以增加过渡金属氧化物层的电阻。 还公开了相关设备。

    Resistive memory devices including selected reference memory cells and methods of operating the same
    56.
    发明申请
    Resistive memory devices including selected reference memory cells and methods of operating the same 审中-公开
    电阻式存储器件包括所选择的参考存储单元及其操作方法

    公开(公告)号：US20070103964A1

    公开(公告)日：2007-05-10

    申请号：US11580766

    申请日：2006-10-13

    Applicant: Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    Inventor： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC: G11C11/00

    CPC classification number: G11C11/1675 ,  G11C11/1673

    Abstract: A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be conducted via a pair of opposing current source transistors located on first and second opposing sides of the first block to provide the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to provide the programming current parallel to the second block.

    Abstract translation: 访问电阻式存储器件的方法可以包括在耦合到第二字线的第二电阻存储器单元块的读取操作期间将预定电压电平施加到耦合到第一电阻存储器单元块的第一字线。编程电流可以 位于第一块的第一和第二相对侧上的一对相对的电流源晶体管导通，以提供编程电流，从而从第一端到第二端跨越与第一块中的电阻式存储单元耦合的位线，并提供 编程电流平行于第二块。

    Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same
    57.
    发明申请
    Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same 有权
    使用过渡金属氧化物层作为数据存储材料层的非易失性存储单元及其制造方法

    公开(公告)号：US20060054950A1

    公开(公告)日：2006-03-16

    申请号：US11179319

    申请日：2005-07-12

    Applicant: In-Gyu Baek ,  Moon-Sook Lee

    Inventor： In-Gyu Baek ,  Moon-Sook Lee

    IPC: H01L29/94

    CPC classification number: H01L27/115 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

    Abstract: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula MxOy. In the chemical formula, the characters “M”, “O”, “x” and “y” indicate transition metal, oxygen, a transitional metal composition and an oxygen composition, respectively. The transition metal oxide layer pattern has excessive transition metal content in comparison to a stabilized transition metal oxide layer pattern. Methods of fabricating the non-volatile memory cells are also provided.

    Abstract translation: 提供了使用过渡金属氧化物层作为数据存储材料层的非易失性存储单元。 非易失性存储单元包括彼此重叠的下电极和上电极。 在下电极和上电极之间设置过渡金属氧化物层图案。 过渡金属氧化物层图案由化学式M X x O Y y表示。 在化学式中，字母“M”，“O”，“x”和“y”分别表示过渡金属，氧，过渡金属组成和氧组成。 与稳定的过渡金属氧化物层图案相比，过渡金属氧化物层图案具有过量的过渡金属含量。 还提供了制造非易失性存储单元的方法。

    Semiconductor devices with vertical structure including data storage layer or pattern
    59.
    发明授权
    Semiconductor devices with vertical structure including data storage layer or pattern 有权
    具有垂直结构的半导体器件包括数据存储层或图案

    公开(公告)号：US08796662B2

    公开(公告)日：2014-08-05

    申请号：US13565830

    申请日：2012-08-03

    Applicant: Seong-Ho Song ,  Chan-Jin Park ,  In-Gyu Baek

    Inventor： Seong-Ho Song ,  Chan-Jin Park ,  In-Gyu Baek

    IPC: H01L29/06

    CPC classification number: H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

    Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.

    Abstract translation: 半导体器件包括第一水平成型图案，设置在第一水平成型图案上的水平电极图案和设置在水平电极图案上的第二水平成型图案。 垂直结构延伸穿过水平图案。 垂直结构包括垂直电极图案，插入在垂直电极图案和水平图案之间的数据存储图案，插入在数据存储图案和第一模制图案之间的第一缓冲图案和插入在数据存储器之间的第二缓冲图案 图案和第二模制图案并且与第一缓冲图案间隔开。

    Semiconductor memory devices
    60.
    发明授权
    Semiconductor memory devices 有权
    半导体存储器件

    公开(公告)号：US08619490B2

    公开(公告)日：2013-12-31

    申请号：US13153749

    申请日：2011-06-06

    Applicant: Hak-soo Yu ,  Hong-sun Hwang ,  Kwan-young Oh ,  In-gyu Baek ,  Jin-hyoung Kwon

    Inventor： Hak-soo Yu ,  Hong-sun Hwang ,  Kwan-young Oh ,  In-gyu Baek ,  Jin-hyoung Kwon

    IPC: G11C8/00

    CPC classification number: G11C5/063

    Abstract: Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array included in the first storage layer or the second storage layer in correspondence to a control signal. A memory capacity of the array included in the first storage layer is different from a memory capacity of the array included in the second storage layer.

    Abstract translation: 半导体存储器件包括第一存储层和第二存储层，每个存储层包括至少一个阵列，以及用于控制对第一存储层和第二存储层的访问的控制层，以便将数据写入或从 该阵列包括在与控制信号对应的第一存储层或第二存储层中。 包括在第一存储层中的阵列的存储器容量不同于包括在第二存储层中的阵列的存储器容量。

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