公开(公告)号：US20090222783A1

公开(公告)日：2009-09-03

申请号：US12039109

申请日：2008-02-28

Applicant: James A. Culp ,  Gregory A. Northrop ,  Ming Yin

Inventor： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal cell or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

Abstract translation: 因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。 特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。 外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。 每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。 内部电池或内部视图包括形成电池组件的规则形状，并定义电池构造细节，并通过构造进行接地规则清洁，或通过仿真或硬件验证。

公开(公告)号：US07473648B2

公开(公告)日：2009-01-06

申请号：US11308106

申请日：2006-03-07

Applicant: Timothy A. Brunner ,  James A. Culp ,  Lars W. Liebmann

Inventor： Timothy A. Brunner ,  James A. Culp ,  Lars W. Liebmann

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76895 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/28123

Abstract: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

Abstract translation: 形成平面CMOS晶体管的方法将形成栅极层的步骤分成用栅极层图案的第一部分图案化抗蚀剂层，然后用栅极图案蚀刻多晶硅的第一步骤。 第二步利用栅极焊盘和局部互连的图像来形成第二抗蚀剂层，然后用栅极焊盘和局部互连的图案蚀刻多晶硅，从而减少来自不同曝光区域的衍射数量和其它串扰。

公开(公告)号：US20080279443A1

公开(公告)日：2008-11-13

申请号：US12182409

申请日：2008-07-30

Applicant: Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

Inventor： Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

IPC: G06K9/74

CPC classification number: G03F7/70441

Abstract: A mask inspection method and system. Provided is a mask fabrication database describing geometrical shapes S to be printed as part of a mask pattern on a reticle to fabricate a mask through use of a mask fabrication tooling. The shapes S appear on the mask as shapes S′ upon being printed. At least one of the shapes S′ may be geometrically distorted relative to a corresponding at least one of the shapes S due to a lack of precision in the mask fabrication tooling. Also provided is a mask inspection database to be used for inspecting the mask after the mask has been fabricated by the mask fabrication tooling. The mask inspection database describes shapes S″ approximating the shapes S′. A geometric distortion between the shapes S′ and S″ is less than a corresponding geometric distortion between the shapes S′ and S.

Abstract translation: 面罩检查方法和系统。 提供了一种掩模制造数据库，其描述要在掩模版上作为掩模图案的一部分打印的几何形状S，以通过使用掩模制造工具来制造掩模。 形状S在印刷时作为形状S'出现在掩模上。 由于在掩模制造工具中缺乏精度，至少一种形状S'可能相对于形状S中的相应的至少一个形状几何失真。 还提供了掩模检查数据库，用于在通过掩模制造工具制造掩模之后检查掩模。 掩模检查数据库描述形状S'近似形状S'。 形状S'和S“之间的几何变形小于形状S'和S之间的对应的几何变形。

公开(公告)号：US08418087B2

公开(公告)日：2013-04-09

申请号：US13371537

申请日：2012-02-13

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US08301290B2

公开(公告)日：2012-10-30

申请号：US12603679

申请日：2009-10-22

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G06F19/00

CPC classification number: G06F17/5068 ,  G06F2217/10

Abstract: Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

Abstract translation: 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。

公开(公告)号：US08219943B2

公开(公告)日：2012-07-10

申请号：US12425603

申请日：2009-04-17

Applicant: John M Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woeltgens

Inventor： John M Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woeltgens

IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract translation: 一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。 布局单元接收表示网格和字形格式的部分的电路描述。 检查单元检查设计的网格和字形部分。 精心设计单元从检查的设计生成目标布局。 数据准备单元准备掩模制作的目标布局。 模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

公开(公告)号：US08161422B2

公开(公告)日：2012-04-17

申请号：US12349108

申请日：2009-01-06

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield ,  Kafai Lai ,  Alan E. Rosenbluth

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield ,  Kafai Lai ,  Alan E. Rosenbluth

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5λ/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROI1 to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.

Abstract translation: 提供了一种用于在用于制造半导体集成电路的光掩模的设计中对光刻工艺进行建模的方法，更具体地说，用于模拟中间范围闪光效应。 对于当点扩散函数具有根据预定标准缓慢变化的斜率时，从约5λ/ NA的第一ROI1到距离ROI2的影响区域（ROI），则至少在从ROI1到ROI2的距离范围内的掩模形状 在计算SOCS卷积之前进行平滑处理。 该方法提供了一种用于以足够的精度模拟中等范围闪光效果的快速方法。

公开(公告)号：US20110166686A1

公开(公告)日：2011-07-07

申请号：US12652409

申请日：2010-01-05

Applicant: James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

Inventor： James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

IPC: G06F17/50 ,  G06G7/66 ,  G06N5/02

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

Abstract translation: 一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二 输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。

公开(公告)号：US20110068436A1

公开(公告)日：2011-03-24

申请号：US12566043

申请日：2009-09-24

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: H01L21/311 ,  H01L21/3213 ,  H01L23/544

CPC classification number: H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3185

Abstract: Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.

Abstract translation: 用于增强不同基底区域中异质特征之间的周长与表面积之比的均匀性的方法和结构。 衬底上的至少一种形状包括有效减少第一衬底区域中的特征与第二衬底区域中的特征之间的周边表面积比的差异的附加边缘。 周边至表面积比的改善的均匀性降低了跨越第一和第二基底区域中的特征沉积的共形层的厚度变化。

公开(公告)号：US07900178B2

公开(公告)日：2011-03-01

申请号：US12039109

申请日：2008-02-28

Applicant: James A. Culp ,  Gregory A. Northrop ,  Ming Yin

Inventor： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal representation or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

Abstract translation: 因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。 特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。 外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。 每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。 内部表示或内部视图包括形成细胞组分的规则形状，并定义细胞结构细节，并通过构造进行基础规则清洁或通过模拟或硬件验证。