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公开(公告)号：US12021959B2
公开(公告)日：2024-06-25
申请号：US17731651
申请日：2022-04-28
Applicant: Mellanox Technologies, Ltd.
Inventor： Igal Kushnir
CPC classification number: H04L7/0016 , G04F10/005 , H03K3/017
Abstract: A system includes a first device, coupled to a link, which transmits a signal having a repeating pattern on one or more paths of the link. The system includes a second device coupled to the link and including one or more circuits and a time-to-digital converter (TDC). The second device is to receive at the one or more circuits the signal. The second device is to determine, by the TDC, a current duty cycle of the signal, the current duty cycle having a first duration associated with a first portion of the signal and a second duration associated with a second portion of the signal. The second device is further to determine the current duty cycle fails to satisfy a condition associated with a target duty cycle in response to determining the current duty cycle of the signal and adjust the current duty cycle to obtain an adjusted duty cycle.
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公开(公告)号：US12019291B2
公开(公告)日：2024-06-25
申请号：US17977103
申请日：2022-10-31
Applicant: Mellanox Technologies, Ltd.
Inventor： Yaniv Kazav , Andrey Ger , Nimer Hazin , Igal Gutman
CPC classification number: G02B6/4284 , G02B6/4256 , G02B6/4269
Abstract: A network interface device which may include: an elongated frame having a first end, a second end, and, between the first and second ends, a top wall, a bottom wall opposing the top wall, a first lateral wall, and a second lateral wall opposing the first lateral wall; wherein the top wall includes: a first longitudinal portion that is adjacent to the first end of the frame; and a second longitudinal portion that is adjacent to the second end of the frame and whose outer surface slopes towards its inner surface in a direction of the second end of the frame.
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公开(公告)号：US20240184709A1
公开(公告)日：2024-06-06
申请号：US18073586
申请日：2022-12-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Liron MULA , Avi URMAN
IPC: G06F12/0893 , H04L9/06
CPC classification number: G06F12/0893 , H04L9/0643
Abstract: A caching system operative in conjunction with a memory and a cache, the caching system comprising a processor to use only a single hash function which compresses K bit memory addresses to H_max bit cache addresses, rather than using plural hash functions, to provide perfect hashing for each of plural applications which utilize plural respective subsets, of different sizes, from among 2{circumflex over ( )}H_max cells in the cache; and at least one logic circuit X which receives, as one of its input operands, an output, H_max bits in length, of the single hash function and which generates, as a logic circuit output, a cache address of length H_select to which at least one K-bit address is mapped where H_max
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公开(公告)号：US20240179029A1
公开(公告)日：2024-05-30
申请号：US18059811
申请日：2022-11-29
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Joseph Boccuzzi , Dotan David Levi
CPC classification number: H04L25/0204 , H04W24/02
Abstract: Approaches in accordance with various embodiments enable communication functionality to be added to an existing hardware component, such as a network interface controller (NIC), data processing unit (DPA), or network switch, rather than requiring an additional component such as a Front Haul Multiplexor (FHM)-type for cellular communications. Such an approach not only avoids the cost and complexity of managing additional hardware components, but can also reduce bandwidth needed for signal transmission. For downlink communications, data can be copied to the relevant radio units of a cell in a single cell deployment architecture to be transmitted to a target client device, such as a cellular handset. For uplink communications, data received from a client device to multiple radio units can undergo decompression and channel estimation before combining the data into a single signal or data stream.
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公开(公告)号：US20240168797A1
公开(公告)日：2024-05-23
申请号：US17988812
申请日：2022-11-17
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Wojciech Wasko , Dotan David Levi , Harsha Deepak Banuli Nanje Gowda , Natan Manevich , Daniel Marcovitch
CPC classification number: G06F9/4881 , G06F1/12 , G06F13/405
Abstract: In one embodiment, a system includes a peripheral data connection bus configured to connect to devices and transfer data between the devices, a scheduling machine configured to connect to the peripheral data connection bus and send a read request message to a first processing device, and the first processing device configured to be connected to the peripheral data connection bus, and responsively to the read request message add a time value to a read response message, and provide the read response message to the scheduling machine, and wherein the scheduling machine is configured to read the time value from the provided read response message and schedule processing of an operation by a second processing device responsively to the read time value.
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Patent Agency Ranking
公开(公告)号：US20240154783A1
公开(公告)日：2024-05-09
申请号：US17983427
申请日：2022-11-09
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko
CPC classification number: H04L7/0008 , H04L7/06 , H04L47/6225
Abstract: In one embodiment, a system includes a network interface controller to receive a first clock-synchronization message from a clock-synchronization leader device and send a second clock-synchronization messages to at least one clock-synchronization follower device, and a processor to execute software to generate the second clock-synchronization message, and generate a control dependency to condition sending the second clock-synchronization message by the network interface controller to the at least one clock-synchronization follower device on the network interface controller receiving the first clock-synchronization message from the clock-synchronization leader device.
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公开(公告)号：US20240154712A1
公开(公告)日：2024-05-09
申请号：US18415883
申请日：2024-01-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC: H04J3/06
CPC classification number: H04J3/0638
Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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公开(公告)号：US20240146664A1
公开(公告)日：2024-05-02
申请号：US17979018
申请日：2022-11-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Gal Yefet , Daniel Marcovitch , Roee Moyal , Gil Bloch , Ariel Shahar , Yossef Itigin
IPC: H04L47/625 , H04L47/62 , H04L47/6275
CPC classification number: H04L47/6255 , H04L47/6225 , H04L47/6275
Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.
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公开(公告)号：US20240143526A1
公开(公告)日：2024-05-02
申请号：US17976909
申请日：2022-10-31
Applicant: Mellanox Technologies, Ltd.
Inventor： Liran Liss , Rabia Loulou , Idan Burstein , Tzuriel Katoa
CPC classification number: G06F13/28 , G06F13/4221
Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.
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60.发明公开公开(公告)号：US20240134970A1
公开(公告)日：2024-04-25
申请号：US17972898
申请日：2022-10-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Itai Levy , Shachar Dor , Parav Kanaiyalal Pandit , Liel Shoshan
CPC classification number: G06F21/552 , G06F21/6218 , G06F2221/034
Abstract: A system includes a data processing unit (DPU) and DPU resource management circuits. A DPU resource management circuit establishes an interface associated with managing resources of the DPU, where establishing the interface is based on another DPU resource management circuit of the system accessing the DPU. The DPU resource management circuit monitors usage of the resources of the DPU based on auditing data provided by the second DPU resource management circuit. In some cases, the DPU resource management circuit may allocate resources of the DPU to an application. The DPU resource management circuit generates a catalog data structure of the resources of the DPU. The catalog data structure includes entries corresponding to resources of the DPU and functions provided by the resources.
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