公开(公告)号：US08505036B2

公开(公告)日：2013-08-06

申请号：US11537531

申请日：2006-09-29

Applicant: Deji Chen ,  Mark J. Nixon ,  Tom Aneweer ,  John R. Shepard ,  Aloysius K. Mok

Inventor： Deji Chen ,  Mark J. Nixon ,  Tom Aneweer ,  John R. Shepard ,  Aloysius K. Mok

IPC: G06F3/00

CPC classification number: G05B19/4186 ,  Y02P90/18 ,  Y02P90/185

Abstract: An application programming interface schema, method and system for communicating between first and second application programming interfaces within a process control system includes processing a call from a first application programming interface for a data request, translating the data request from the first application programming interface into one or more methods of a unified application programming interface, and implementing the one or more methods of the unified application programming interface with a second application programming interface. A first unified layer receives a transmission request from a proprietary application programming interface, and translates the transmission request into one or more methods of a unified application programming interface. A second unified layer implements methods of the unified application programming interface with the wireless network application programming interface.

Abstract translation: 用于在过程控制系统内的第一和第二应用程序编程接口之间进行通信的应用编程接口架构，方法和系统包括处理来自第一应用编程接口的用于数据请求的调用，将数据请求从第一应用编程接口转换成一个 或更多的统一应用程序编程接口的方法，以及使用第二应用编程接口来实现统一应用编程接口的一个或多个方法。 第一统一层从专用应用编程接口接收传输请求，并将传输请求转换成统一应用编程接口的一个或多个方法。 第二统一层利用无线网络应用编程接口实现统一应用编程接口的方法。

公开(公告)号：US08358525B2

公开(公告)日：2013-01-22

申请号：US12898205

申请日：2010-10-05

Applicant: Daniel R. Shepard

Inventor： Daniel R. Shepard

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G06K5/04 ,  G11C5/025 ,  G11C7/00 ,  G11C16/04 ,  G11C29/006 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/5006 ,  H01L21/84 ,  H01L22/32 ,  H01L27/10 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

公开(公告)号：US20120296448A1

公开(公告)日：2012-11-22

申请号：US13111560

申请日：2011-05-19

Applicant: James R. Balentine ,  Andre A. Dicaire ,  Cindy A. Scott ,  Donald Robert Lattimer ,  Kenneth Schibler ,  John R. Shepard ,  Larry O. Jundt

Inventor： James R. Balentine ,  Andre A. Dicaire ,  Cindy A. Scott ,  Donald Robert Lattimer ,  Kenneth Schibler ,  John R. Shepard ,  Larry O. Jundt

IPC: G05B15/02

CPC classification number: G05B19/0426 ,  G05B19/409 ,  G05B2219/23008 ,  G05B2219/32122 ,  G05B2219/32152 ,  Y02P90/14

Abstract: A process control system coordinates with an associated asset management system to implement a plant safety mechanism and, in particular, to prevent unintended changes to, or otherwise undesired operation of, one or more process control equipment resources in a process plant. A maintenance technician uses the asset management system to request access to one or more of the process control equipment resources. A process operator receives the request via the process control system and grants or denies the request. Process control equipment resources for which a process operator grants a request are inoperable, in part or in whole, by the process control system. Upon completion of the maintenance task, the maintenance technician requests to return control of the process control equipment resource to the process operator. The return is complete when the process operator acknowledges the return of the resource to the process control system.

Abstract translation: 过程控制系统与相关联的资产管理系统协调以实现工厂安全机制，特别是防止过程工厂中的一个或多个过程控制设备资源的意外变化或以其他方式不期望的操作。 维护技术人员使用资产管理系统来请求访问一个或多个过程控制设备资源。 过程操作者通过过程控制系统接收请求，并授予或拒绝该请求。 过程控制系统对过程控制设备资源进行过程控制系统的部分或全部不可操作。 在完成维护任务后，维护技术人员请求将过程控制设备资源的控制返回给过程操作员。 当过程操作员确认资源返回到过程控制系统时，返回完成。

公开(公告)号：US20110124708A1

公开(公告)日：2011-05-26

申请号：US12967121

申请日：2010-12-14

Applicant: Allan R. Shepard ,  Jon E. Chatterton ,  Abbot F. Clark

Inventor： Allan R. Shepard ,  Jon E. Chatterton ,  Abbot F. Clark

IPC: A61K31/713 ,  A61P27/02 ,  A61P9/12

CPC classification number: C12N15/1137 ,  C12N15/1138 ,  C12N2310/111 ,  C12N2310/14 ,  C12N2310/53 ,  C12Y301/01007 ,  C12Y306/03009 ,  C12Y402/01001

Abstract: RNA interference is provided for inhibition of ocular hypertension target mRNA expression for lowering elevated intraocular pressure in patients with open-angle glaucoma or ocular hypertension. Ocular hypertension targets include carbonic anhydrase II, IV, and XII; β1- and β2 adrenergic receptors; acetylcholinesterase; Na+/K+-ATPase; and Na—K-2Cl cotransporter. Ocular hypertension is treated by administering interfering RNAs of the present invention.

Abstract translation: 提供RNA干扰用于抑制眼高血压靶mRNA表达，以降低开角型青光眼或高眼压患者眼内压升高。 眼睛高血压指标包括碳酸酐酶II，IV和XII; 1和β2肾上腺素能受体; 乙酰胆碱酯酶; Na + / K + -ATPase; 和Na-K-2Cl共转运蛋白。 通过施用本发明的干扰RNA来治疗眼高血压。

公开(公告)号：US20110098314A1

公开(公告)日：2011-04-28

申请号：US12941639

申请日：2010-11-08

Applicant: Mark R. Hellberg ,  Debra L. Fleenor ,  Allan R. Shepard ,  Iok-Hou Pang

Inventor： Mark R. Hellberg ,  Debra L. Fleenor ,  Allan R. Shepard ,  Iok-Hou Pang

IPC: A61K31/505 ,  A61K31/351 ,  A61K31/22 ,  A61K31/404 ,  A61K31/40 ,  A61K31/47 ,  A61P27/02

CPC classification number: A61K31/00 ,  A61K31/225 ,  A61K31/366 ,  A61K31/401

Abstract: The use of HMG-CoA reductase inhibitors (e.g., statins) to treat glaucoma, control intraocular pressure, preserve the trabecular meshwork, protect against ocular neurodegeneration and/or protect against glaucomatous retinopathy is described. The preferred HMG-CoA reductase inhibitors, which are statins having an RI value of 0.2 to 0.7 (e.g., pravastatin), are administered via topical application to the affected eye(s) of the patient.

Abstract translation: 描述了使用HMG-CoA还原酶抑制剂（例如他汀类药物）来治疗青光眼，控制眼内压，保留小梁网，防止眼神经变性和/或防止青光眼性视网膜病变。 优选的HMG-CoA还原酶抑制剂，其为RI值为0.2至0.7的他汀类（例如，普伐他汀），通过局部施用施用于患者的受影响的眼睛。

公开(公告)号：US20100247548A1

公开(公告)日：2010-09-30

申请号：US12796748

申请日：2010-06-09

Applicant: Allan R. Shepard ,  Debra L. Fleenor ,  Abbot F. Clark ,  Najam A. Sharif

Inventor： Allan R. Shepard ,  Debra L. Fleenor ,  Abbot F. Clark ,  Najam A. Sharif

IPC: A61K39/395 ,  A61K38/00 ,  A61K31/70 ,  A61K31/7088 ,  A61K31/175 ,  A61P27/02

CPC classification number: A61K31/7088 ,  A61K31/70 ,  A61K38/00

Abstract: Antagonists of cation-independent mannose 6-phosphate/insulin-like growth factor-II receptor are provided for attenuation of CTGF signaling in a method of down-regulation of receptor signaling and downstream decreased signaling of connective tissue growth factor in ocular disorders involving inappropriate CTGF signaling. Ocular disorders involving inappropriate CTGF signaling include ocular hypertension, glaucoma, glaucomatous retinopathy, optic neuropathy, macular degeneration, diabetic retinopathy, choroidal neovascularization, and proliferative vitreoretinopathy, for example. Such disorders are treated by administering antagonists of the present invention.

Abstract translation: 提供阳离子非依赖性甘露糖-6-磷酸/胰岛素样生长因子-II受体的拮抗剂用于在受体信号下调的方法中降低CTGF信号传导，并且下游减少涉及不适当CTGF的眼部疾病中结缔组织生长因子的信号转导 信令。 涉及不适当CTGF信号的眼部疾病包括例如高眼压症，青光眼，青光眼性视网膜病变，视神经病变，黄斑变性，糖尿病性视网膜病变，脉络膜新生血管形成和增殖性玻璃体视网膜病变。 通过施用本发明的拮抗剂治疗此类病症。

公开(公告)号：USRE41733E1

公开(公告)日：2010-09-21

申请号：US09821182

申请日：2001-03-29

Applicant: Daniel R. Shepard

Inventor： Daniel R. Shepard

IPC: G11C17/06

CPC classification number: G11C17/10 ,  G06F17/00 ,  G11C8/04 ,  G11C17/00 ,  G11C17/06 ,  H01L27/1021 ,  H01L27/112

Abstract: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable scalable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

Abstract translation: 提供了只读数据存储和检索装置，其没有移动部件并且需要非常低的功率。 可以顺序完成寻址，其中地址自动增加或可以随机完成。 通过使用在两个坐标方向上寻址的高度对称的二极管矩阵来实现高密度存储; 其对称性使得双寻址整流器存储（DRS）阵列非常可扩展，特别是在作为集成电路时。 为了获得更大的存储灵活性，可将多个数字整流器存储阵列并入设备中，其中一个或多个可以被制造为可移除和可互换的。

公开(公告)号：US20100164543A1

公开(公告)日：2010-07-01

申请号：US12643287

申请日：2009-12-21

Applicant: Daniel R. Shepard

Inventor： Daniel R. Shepard

IPC: H03K19/21 ,  G11C11/00 ,  H01L21/98 ,  G06F7/50

CPC classification number: H03K19/21 ,  G06F7/501 ,  G06F7/502 ,  Y10T29/49155

Abstract: In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit.

Abstract translation: 在各种实施例中，加法器电路包括多个晶体管，所有晶体管都是从由NMOS晶体管和PMOS晶体管组成的组中选择的单一类型的晶体管，并且耗散不比等效CMOS电路多的功率。

公开(公告)号：US20100157646A1

公开(公告)日：2010-06-24

申请号：US12639599

申请日：2009-12-16

Applicant: Daniel R. Shepard

Inventor： Daniel R. Shepard

IPC: G11C5/02 ,  G11C8/10 ,  G11C8/00 ,  G11C7/00 ,  H01S4/00

CPC classification number: G11C7/02 ,  G11C29/83 ,  Y10T29/49002

Abstract: A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection.

Abstract translation: 具有沿着多个大致平行的线路设置的多个存储位置的存储器件包括连接到线路的用于选择一条线路的解码器电路，并且连接到每条线路，用于选择性地防止线路 在选线期间通电。

公开(公告)号：US20090257269A1

公开(公告)日：2009-10-15

申请号：US12417245

申请日：2009-04-02

Applicant: Daniel R. Shepard

Inventor： Daniel R. Shepard

IPC: G11C11/00 ,  H01S4/00 ,  H03H11/24 ,  G11C5/14

CPC classification number: G11C11/412

Abstract: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.

Abstract translation: 诸如锁存器或定序器的电子电路包括多个晶体管，所有晶体管都是NMOS晶体管或PMOS晶体管，并且耗散小于或大致相等量的功率作为等效CMOS电路。