公开(公告)号：US20110013258A1

公开(公告)日：2011-01-20

申请号：US12654682

申请日：2009-12-29

Applicant: Hwan-Soo Lee ,  Yongsoo Oh ,  Sang Moon Lee ,  Hye Yeon Cha ,  Jeong Bok Kwak

Inventor： Hwan-Soo Lee ,  Yongsoo Oh ,  Sang Moon Lee ,  Hye Yeon Cha ,  Jeong Bok Kwak

IPC: G02F1/167 ,  H01J9/20

CPC classification number: G02B26/026 ,  G02F1/17

Abstract: The present invention relates to a manufacturing method of an electronic paper display device and an electronic paper display device manufactured therefrom.The manufacturing method of the electronic paper display device may include forming a first auxiliary first dielectric layer on a first substrate; disposing electronic balls on the first auxiliary first dielectric layer; forming a second auxiliary first dielectric layer that fixes the electronic balls by curing the first auxiliary first dielectric layer; forming an auxiliary second dielectric layer on the second auxiliary first dielectric layer including the electronic balls; forming first and second dielectric layers by curing the second auxiliary first dielectric layer and the auxiliary second dielectric layer; and bonding the first substrate including the second dielectric layer to a second substrate.

Abstract translation: 本发明涉及电子纸显示装置及其制造的电子纸显示装置的制造方法。 电子纸显示装置的制造方法可以包括在第一基板上形成第一辅助第一介电层; 在第一辅助第一介电层上设置电子球; 形成通过固化所述第一辅助第一介电层来固定所述电子球的第二辅助第一电介质层; 在包括电子球的第二辅助第一电介质层上形成辅助第二电介质层; 通过固化所述第二辅助第一介电层和所述辅助第二介电层来形成第一和第二电介质层; 以及将包括所述第二介电层的所述第一基板结合到第二基板。

公开(公告)号：US20100047528A1

公开(公告)日：2010-02-25

申请号：US12544524

申请日：2009-08-20

Applicant: Hwan-Soo Lee ,  Yongsoo Oh ,  Sang-Moon Lee ,  Jeong-Bok Kwak

Inventor： Hwan-Soo Lee ,  Yongsoo Oh ,  Sang-Moon Lee ,  Jeong-Bok Kwak

IPC: B32B3/00 ,  B32B37/00

CPC classification number: G02F1/167 ,  G02B26/026 ,  G02F2001/1672 ,  Y10T428/24612

Abstract: An electronic paper display device and a method of manufacturing the electronic paper display device are disclosed. The method can include forming a plurality of relievo patterns on a lower board, in which the relievo patterns are formed to be independent and separated from one another, disposing a display unit in between the plurality of relievo patterns, and attaching an upper board on the plurality of relievo patterns such that the display unit is covered. In accordance with an embodiment of the present invention, the method can improve the freedom of disposing the display units by allowing partition walls to form only at areas to fix the display units.

Abstract translation: 公开了电子纸显示装置和电子纸显示装置的制造方法。 该方法可以包括在下板上形成多个减压图案，其中，所述减震图案被形成为彼此独立且分离，将显示单元设置在所述多个减速图案之间，并且将上板安装在 多个解码图案使得显示单元被覆盖。 根据本发明的一个实施例，该方法可以通过仅在限定显示单元的区域处形成分隔壁而提高布置显示单元的自由度。

公开(公告)号：US20090095981A1

公开(公告)日：2009-04-16

申请号：US12073308

申请日：2008-03-04

Applicant: Dong-hun Kang ,  Sang-moon Lee ,  Joong S. Jeong ,  Kwang-hyeon Baik

Inventor： Dong-hun Kang ,  Sang-moon Lee ,  Joong S. Jeong ,  Kwang-hyeon Baik

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/78

Abstract: Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. The CMOS device comprises an epi-layer that may be formed on a substrate; a first semiconductor layer and a second semiconductor layer that may be formed on different regions of the epi-layer, respectively; and a PMOS transistor and a NMOS transistor that may be formed on the first and second semiconductor layers, respectively.

Abstract translation: 提供互补金属氧化物半导体（CMOS）器件及其制造方法。 CMOS器件包括可以形成在衬底上的外延层; 可以分别形成在外延层的不同区域上的第一半导体层和第二半导体层; 以及可以分别形成在第一和第二半导体层上的PMOS晶体管和NMOS晶体管。

公开(公告)号：US07473153B2

公开(公告)日：2009-01-06

申请号：US11064966

申请日：2005-02-25

Applicant: Hyoung Dong Kang ,  Hyun Chul Jung ,  Sang Moon Lee ,  Jong Myeon Lee

Inventor： Hyoung Dong Kang ,  Hyun Chul Jung ,  Sang Moon Lee ,  Jong Myeon Lee

IPC: H01J9/24

CPC classification number: H01J9/025 ,  B82Y10/00 ,  B82Y30/00 ,  H01J2201/30469

Abstract: A process for fabricating a field emitter electrode includes: impregnating a cathode and anode in an electrolyte containing carbon nanotubes dispersed therein and applying a predetermined voltage to the cathode and anode so as to deposit carbon nanotubes on a substrate provided on the anode; recovering the substrate and applying a conductive polymer onto the surface of the substrate having carbon nanotubes deposited thereon; and heat treating the conductive polymer having carbon nanotubes deposited thereon, so as to completely cure it.

Abstract translation: 制造场致发射电极的方法包括：在分散在其中的含有碳纳米管的电解质中浸渍阴极和阳极，并向阴极和阳极施加预定电压，以将碳纳米管沉积在设置在阳极上的衬底上; 回收衬底并将导电聚合物施加到其上沉积有碳纳米管的衬底的表面上; 并对其上沉积有碳纳米管的导电聚合物进行热处理，以使其完全固化。

公开(公告)号：US20070066094A1

公开(公告)日：2007-03-22

申请号：US11517493

申请日：2006-09-07

Applicant: Jung-hye Kim ,  Sang-moon Lee ,  Il-chan Park ,  Byung-wook Ahn

Inventor： Jung-hye Kim ,  Sang-moon Lee ,  Il-chan Park ,  Byung-wook Ahn

IPC: H01R12/00

CPC classification number: H01R13/2421 ,  H01L24/81 ,  H01L2924/14 ,  H01R2201/20 ,  H05K3/325 ,  H05K3/3457 ,  H05K2201/10734 ,  H05K2203/0278 ,  H01L2924/00

Abstract: Provided are an integrated circuit (IC) package having balls designed to minimize contact resistance, a test apparatus for testing the IC package, and a method of manufacturing the IC package. The IC package is a ball grid array (BGA) package including solder balls, the solder balls having substantially flat bottoms. The balls of the BGA package are Pb-free balls, and are polished using a mechanical polishing method or a chemical polishing method to have the substantially flat bottoms. The test apparatus includes a plurality of channels, a test board having a wiring pattern connected to the channels, and an IC socket having a plurality of Pogo pins respectively connected to lands of the wiring pattern. The top ends of the Pogo pins of the IC socket are made substantially flat to increase the area that contacts the substantially flat bottom surfaces of the BGA package.

Abstract translation: 提供了具有设计成使接触电阻最小化的球的集成电路（IC）封装，用于测试IC封装的测试装置以及IC封装的制造方法。 IC封装是包括焊球的球栅阵列（BGA）封装，焊球具有基本平坦的底部。 BGA封装的球是无铅球，并且使用机械抛光方法或化学抛光方法抛光以具有基本平坦的底部。 测试装置包括多个通道，具有连接到通道的布线图案的测试板，以及分别连接到布线图案的平台的多个Pogo引脚的IC插座。 IC插座的Pogo引脚的顶端基本上平坦，以增加接触BGA封装的基本平坦的底表面的面积。

公开(公告)号：US20060251136A1

公开(公告)日：2006-11-09

申请号：US11417193

申请日：2006-05-04

Applicant: Sang-moon Lee

Inventor： Sang-moon Lee

IPC: H01S5/00 ,  H01S3/091 ,  H01S3/08 ,  H01S3/092

CPC classification number: H01S5/183 ,  H01S3/109 ,  H01S5/0207 ,  H01S5/026 ,  H01S5/041 ,  H01S5/1085 ,  H01S5/14 ,  H01S5/18 ,  H01S5/4043

Abstract: Provided is a vertical external cavity surface emitting laser (VECSEL) in which a pump laser is integrated with the rest of the VECSEL as a single body. The VECSEL includes: a first active layer that has a quantum well structure and generates light with a first wavelength; a reflection layer formed on a first surface of the first active layer; an external mirror that is separated by a predetermined distance from a second surface of the first active layer, transmits a portion of light generated by the first active layer to the outside, and reflects the rest of the light generated by the first active layer to be absorbed by the first active layer; and a pump laser disposed on the reflection layer as a single body to provide light with a second wavelength which is shorter than the first wavelength to the first active layer for optical pumping.

公开(公告)号：US07127134B2

公开(公告)日：2006-10-24

申请号：US10864058

申请日：2004-06-09

Applicant: Byung-Kwon Kang ,  In Kim ,  Yu-Dong Bae ,  Byeong-Hoon Park ,  Sang-Moon Lee ,  Young-Hyun Kim

Inventor： Byung-Kwon Kang ,  In Kim ,  Yu-Dong Bae ,  Byeong-Hoon Park ,  Sang-Moon Lee ,  Young-Hyun Kim

IPC: G02B6/12 ,  G02B6/10 ,  G02B6/42 ,  H01S5/00 ,  H01L27/15

CPC classification number: G02B6/26 ,  H01S5/0264

Abstract: A monolithic integrated semiconductor optical element is disclosed. The semiconductor optical element including a substrate, a first waveguide, formed on the substrate, including a first active layer for generating light, and a semi-insulating, grown on the substrate so as to surround a perimeter of the first waveguide layer, including a window area for diffusing the light outputted from the first waveguide and outputting the diffused light. The semiconductor optical elements also includes at least one second waveguide, formed in the window area close to the first waveguide, including a second active layer for detecting a part of the light diffused by the window area.

Abstract translation: 公开了一种单片集成半导体光学元件。 所述半导体光学元件包括基板，形成在所述基板上的第一波导，所述基板包括用于产生光的第一有源层和半绝缘层，所述第一有源层在所述基板上生长以包围所述第一波导层的周边， 窗口区域，用于扩散从第一波导输出的光并输出漫射光。 半导体光学元件还包括形成在靠近第一波导的窗口区域中的至少一个第二波导，包括用于检测由窗口区域扩散的光的一部分的第二有源层。

公开(公告)号：US20060166383A1

公开(公告)日：2006-07-27

申请号：US11336687

申请日：2006-01-20

Applicant: Sang-moon Lee ,  Young-bu Kim ,  Jung-hye Kim

Inventor： Sang-moon Lee ,  Young-bu Kim ,  Jung-hye Kim

IPC: H01L21/66

CPC classification number: H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/5448 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The semiconductor substrate is aligned with reference to the reference semiconductor chip, so that an electrical die sorting test can be performed on the semiconductor chips on the semiconductor substrate.

公开(公告)号：US07016558B2

公开(公告)日：2006-03-21

申请号：US10792621

申请日：2004-03-03

Applicant: Young-Hyun Kim ,  In Kim ,  Sang-Moon Lee ,  Byung-Ok Jeon

Inventor： Young-Hyun Kim ,  In Kim ,  Sang-Moon Lee ,  Byung-Ok Jeon

IPC: G02B6/12

CPC classification number: G02B6/1342 ,  G02B6/12004 ,  H01S5/0265 ,  H01S5/3072

Abstract: An integrated optical device having at least two optical devices integrated therein and a method of fabricating the integrated optical device are provided. To fabricate an integrated optical device having optically connected and electrically isolated first and second optical devices on a substrate of a first conductive type, an active layer and a clad layer of a second conductive type are first formed in a mesa structure on the substrate, an SI clad layer is then formed on the substrate surrounding the clad layer of the second conductive type and the active layer, and finally first and second conductive layers are formed into trenches by diffusing a dopant of the second conductive type into the SI clad layer in areas corresponding to the first and second optical devices.

Abstract translation: 提供一种其中集成有至少两个光学器件的集成光学器件和制造该集成光学器件的方法。 为了制造在第一导电类型的衬底上具有光学连接和电隔离的第一和第二光学器件的集成光学器件，首先在衬底上的台面结构中形成第二导电类型的有源层和覆盖层， 然后在围绕第二导电类型和有源层的包覆层的衬底上形成SI包覆层，最后通过将第二导电类型的掺杂剂扩散到区域中的SI包覆层中而将第一和第二导电层形成沟槽 对应于第一和第二光学装置。

公开(公告)号：US20050129368A1

公开(公告)日：2005-06-16

申请号：US10864058

申请日：2004-06-09

Applicant: Byung-Kwon Kang ,  In Kim ,  Yu-Dong Bae ,  Byeong-Hoon Park ,  Sang-Moon Lee ,  Young-Hyun Kim

Inventor： Byung-Kwon Kang ,  In Kim ,  Yu-Dong Bae ,  Byeong-Hoon Park ,  Sang-Moon Lee ,  Young-Hyun Kim

IPC: G02B6/122 ,  G02B6/26 ,  H01L31/12 ,  H01S5/026 ,  G02B6/42

CPC classification number: G02B6/26 ,  H01S5/0264

Abstract: A monolithic integrated semiconductor optical element is disclosed. The semiconductor optical element including a substrate, a first waveguide, formed on the substrate, including a first active layer for generating light, and a semi-insulating, grown on the substrate so as to surround a perimeter of the first waveguide layer, including a window area for diffusing the light outputted from the first waveguide and outputting the diffused light. The semiconductor optical elements also includes at least one second waveguide, formed in the window area close to the first waveguide, including a second active layer for detecting a part of the light diffused by the window area.

Abstract translation: 公开了一种单片集成半导体光学元件。 所述半导体光学元件包括基板，形成在所述基板上的第一波导，所述基板包括用于产生光的第一有源层和半绝缘层，所述第一有源层在所述基板上生长以包围所述第一波导层的周边， 窗口区域，用于扩散从第一波导输出的光并输出漫射光。 半导体光学元件还包括形成在靠近第一波导的窗口区域中的至少一个第二波导，包括用于检测由窗口区域扩散的光的一部分的第二有源层。