公开(公告)号：US08878211B2

公开(公告)日：2014-11-04

申请号：US13327647

申请日：2011-12-15

Applicant: Sung Min Hwang ,  Kwang Hyeon Baik ,  Yong Gon Seo ,  Hyung Do Yoon ,  Jae Hyoun Park

Inventor： Sung Min Hwang ,  Kwang Hyeon Baik ,  Yong Gon Seo ,  Hyung Do Yoon ,  Jae Hyoun Park

IPC: H01L33/16 ,  H01L21/02 ,  H01L33/00 ,  H01L33/22

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02639 ,  H01L33/007 ,  H01L33/22

Abstract: Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.

Abstract translation: 提供了异质衬底，使用其的氮化物基半导体器件及其制造方法，以在非均相衬底的非极性或半极性平面上形成高质量非极性或半极性氮化物层 通过调整晶体生长模式。 准备具有非极性面和半极性面之一的基底基板，在基底基板的平面上形成氮化物系成核层。 第一缓冲层在垂直方向上比在成核层上的横向方向上生长得更快。 横向生长层在横向上比在第一缓冲层上比垂直方向上生长得更快。 在侧生长层上形成第二缓冲层。 可以在第一缓冲层上的横向生长层和第二缓冲层之间形成具有多个孔的氮化硅层。

公开(公告)号：US20120086017A1

公开(公告)日：2012-04-12

申请号：US13327647

申请日：2011-12-15

Applicant: Sung Min HWANG ,  Kwang Hyeon BAIK ,  Yong Gon SEO ,  Hyung Do YOON ,  Jae Hyoun PARK

Inventor： Sung Min HWANG ,  Kwang Hyeon BAIK ,  Yong Gon SEO ,  Hyung Do YOON ,  Jae Hyoun PARK

IPC: H01L29/22 ,  H01L21/20 ,  H01L29/06

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02639 ,  H01L33/007 ,  H01L33/22

Abstract: Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.

Abstract translation: 提供了异质衬底，使用其的氮化物基半导体器件及其制造方法，以在非均相衬底的非极性或半极性平面上形成高质量非极性或半极性氮化物层 通过调整晶体生长模式。 准备具有非极性面和半极性面之一的基底基板，在基底基板的平面上形成氮化物系成核层。 第一缓冲层在垂直方向上比在成核层上的横向方向上生长得更快。 横向生长层在横向上比在第一缓冲层上比垂直方向上生长得更快。 在侧生长层上形成第二缓冲层。 可以在第一缓冲层上的横向生长层和第二缓冲层之间形成具有多个孔的氮化硅层。

公开(公告)号：US08013354B2

公开(公告)日：2011-09-06

申请号：US11737479

申请日：2007-04-19

Applicant: Jeong-wook Lee ,  Jin-seo Im ,  Bok-ki Min ,  Kwang-hyeon Baik ,  Heon-su Jeon

Inventor： Jeong-wook Lee ,  Jin-seo Im ,  Bok-ki Min ,  Kwang-hyeon Baik ,  Heon-su Jeon

IPC: H01L29/22

CPC classification number: H01L33/22 ,  H01L33/007

Abstract: A semiconductor light emitting device having a multiple pattern structure greatly increases light extraction efficiency. The semiconductor light emitting device includes a substrate and a semiconductor layer, an active layer, and an electrode layer formed on the substrate, a first pattern defining a first corrugated structure between the substrate and the semiconductor layer, and a second pattern defining a second corrugated structure on the first corrugated structure of the first pattern.

Abstract translation: 具有多重图案结构的半导体发光器件大大提高了光提取效率。 半导体发光器件包括衬底和半导体层，有源层和形成在衬底上的电极层，在衬底和半导体层之间限定第一波纹结构的第一图案和限定第二波纹状的第二图案 结构上第一个波纹结构的第一个图案。

公开(公告)号：US20100136790A1

公开(公告)日：2010-06-03

申请号：US12591534

申请日：2009-11-23

Applicant: Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

Inventor： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

IPC: H01L21/302

CPC classification number: H01L21/0337

Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Abstract translation: 一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个 第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻 掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第 第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层 他的间隔。

公开(公告)号：US20090095981A1

公开(公告)日：2009-04-16

申请号：US12073308

申请日：2008-03-04

Applicant: Dong-hun Kang ,  Sang-moon Lee ,  Joong S. Jeong ,  Kwang-hyeon Baik

Inventor： Dong-hun Kang ,  Sang-moon Lee ,  Joong S. Jeong ,  Kwang-hyeon Baik

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/78

Abstract: Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. The CMOS device comprises an epi-layer that may be formed on a substrate; a first semiconductor layer and a second semiconductor layer that may be formed on different regions of the epi-layer, respectively; and a PMOS transistor and a NMOS transistor that may be formed on the first and second semiconductor layers, respectively.

Abstract translation: 提供互补金属氧化物半导体（CMOS）器件及其制造方法。 CMOS器件包括可以形成在衬底上的外延层; 可以分别形成在外延层的不同区域上的第一半导体层和第二半导体层; 以及可以分别形成在第一和第二半导体层上的PMOS晶体管和NMOS晶体管。

公开(公告)号：US20080038857A1

公开(公告)日：2008-02-14

申请号：US11802482

申请日：2007-05-23

Applicant: Kyoung-kook Kim ,  Kwang-ki Choi ,  June-o Song ,  Suk-ho Yoon ,  Kwang-hyeon Baik ,  Hyun-soo Kim

Inventor： Kyoung-kook Kim ,  Kwang-ki Choi ,  June-o Song ,  Suk-ho Yoon ,  Kwang-hyeon Baik ,  Hyun-soo Kim

IPC: H01L21/311

CPC classification number: H01L33/0079 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02439 ,  H01L21/02472 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02664 ,  H01S5/0213 ,  H01S5/0217

Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.

Abstract translation: 提供了一种制造具有提高的效率和增加的输出特性的氮化物基半导体发光器件的方法。 该方法可以包括在衬底上形成具有湿蚀刻性质的牺牲层，在牺牲层上形成保护层，在用于晶体生长的反应气体气氛中保护牺牲层，并且促进要形成的半导体层的外延生长 在保护层上，在保护层上形成包括n型半导体层，有源层和p型半导体层的半导体器件，并且通过湿式蚀刻牺牲层从半导体器件去除衬底。

公开(公告)号：US08518723B2

公开(公告)日：2013-08-27

申请号：US12591534

申请日：2009-11-23

Applicant: Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

Inventor： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

IPC: H01L21/302

CPC classification number: H01L21/0337

Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Abstract translation: 一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个 第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层来形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻 掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第 第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层 他的间隔。

公开(公告)号：US07989244B2

公开(公告)日：2011-08-02

申请号：US11802482

申请日：2007-05-23

Applicant: Kyoung-kook Kim ,  Kwang-ki Choi ,  June-o Song ,  Suk-ho Yoon ,  Kwang-hyeon Baik ,  Hyun-soo Kim

Inventor： Kyoung-kook Kim ,  Kwang-ki Choi ,  June-o Song ,  Suk-ho Yoon ,  Kwang-hyeon Baik ,  Hyun-soo Kim

IPC: H01L21/00

CPC classification number: H01L33/0079 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02439 ,  H01L21/02472 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02664 ,  H01S5/0213 ,  H01S5/0217

Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.

Abstract translation: 提供了一种制造具有提高的效率和增加的输出特性的氮化物基半导体发光器件的方法。 该方法可以包括在衬底上形成具有湿蚀刻性质的牺牲层，在牺牲层上形成保护层，在用于晶体生长的反应气体气氛中保护牺牲层，并且促进要形成的半导体层的外延生长 在保护层上，在保护层上形成包括n型半导体层，有源层和p型半导体层的半导体器件，并且通过湿式蚀刻牺牲层从半导体器件去除衬底。

公开(公告)号：US20070262330A1

公开(公告)日：2007-11-15

申请号：US11737479

申请日：2007-04-19

Applicant: Jeong-wook LEE ,  Jin-seo IM ,  Bok-ki MIN ,  Kwang-hyeon BAIK ,  Heon-su JEON

Inventor： Jeong-wook LEE ,  Jin-seo IM ,  Bok-ki MIN ,  Kwang-hyeon BAIK ,  Heon-su JEON

IPC: H01L33/00

CPC classification number: H01L33/22 ,  H01L33/007

Abstract: A semiconductor light emitting device having a multiple pattern structure greatly increases light extraction efficiency. The semiconductor light emitting device includes a substrate and a semiconductor layer, an active layer, and an electrode layer formed on the substrate, a first pattern defining a first corrugated structure between the substrate and the semiconductor layer, and a second pattern defining a second corrugated structure on the first corrugated structure of the first pattern.

Abstract translation: 具有多重图案结构的半导体发光器件大大提高了光提取效率。 半导体发光器件包括衬底和半导体层，有源层和形成在衬底上的电极层，在衬底和半导体层之间限定第一波纹状结构的第一图案和限定第二波纹状的第二图案 结构上第一个波纹结构的第一个图案。