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    Method Of Programming A Split-Gate Flash Memory Cell With Erase Gate
    51.
    发明申请
    Method Of Programming A Split-Gate Flash Memory Cell With Erase Gate 审中-公开

    公开(公告)号：US20200066738A1

    公开(公告)日：2020-02-27

    申请号：US16209515

    申请日：2018-12-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Yuri Tkachev ,  Alexander Kotov ,  Nhan Do

    IPC: H01L27/11521 ,  H01L29/788 ,  G11C16/04

    Abstract: A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.

    POWER LINE COMPENSATION FOR FLASH MEMORY SENSE AMPLIFIERS
    56.
    发明申请
    POWER LINE COMPENSATION FOR FLASH MEMORY SENSE AMPLIFIERS 审中-公开

    公开(公告)号：US20190355420A1

    公开(公告)日：2019-11-21

    申请号：US16526987

    申请日：2019-07-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran

    IPC: G11C16/04 ,  G11C16/28

    Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.

    Array of three-gate flash memory cells with individual memory cell read, program and erase
    58.
    发明授权
    Array of three-gate flash memory cells with individual memory cell read, program and erase 有权

    公开(公告)号：US10460811B2

    公开(公告)日：2019-10-29

    申请号：US16387377

    申请日：2019-04-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

    IPC: G11C11/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04

    Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

    System And Method For Storing And Retrieving Multibit Data In Non-volatile Memory Using Current Multipliers
    59.
    发明申请
    System And Method For Storing And Retrieving Multibit Data In Non-volatile Memory Using Current Multipliers 审中-公开

    公开(公告)号：US20190206486A1

    公开(公告)日：2019-07-04

    申请号：US16213860

    申请日：2018-12-07

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C2211/5641

    Abstract: A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. Circuitry is configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells. Circuitry is configured to sum the multiplied read values. The read values can be electrical currents, electrical voltages or numerical values. Alternatively, added constant values can be used instead of multipliers. The multipliers or constants can be applied to read currents from individual cells, or read currents on entire bit lines.

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