公开(公告)号：US20200013786A1

公开(公告)日：2020-01-09

申请号：US16028244

申请日：2018-07-05

Applicant: Silicon Storage Technology, Inc.

Inventor： SERGUEI JOURBA ,  CATHERINE DECOBERT ,  FENG ZHOU ,  JINHO KIM ,  XIAN LIU ,  NHAN DO

IPC: H01L27/11524 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088

Abstract: A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

公开(公告)号：US20230101585A1

公开(公告)日：2023-03-30

申请号：US17576754

申请日：2022-01-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Yuri Tkachev ,  JINHO KIM ,  CYNTHIA FUNG ,  GILLES FESTES ,  BERNARD BERTELLO ,  PARVIZ GHAZAVI ,  BRUNO VILLARD ,  JEAN FRANCOIS THIERY ,  CATHERINE DECOBERT ,  SERGUEI JOURBA ,  FAN LUO ,  LATT TEE ,  NHAN DO

IPC: G11C29/50

Abstract: A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

公开(公告)号：US20220231037A1

公开(公告)日：2022-07-21

申请号：US17716950

申请日：2022-04-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  CATHERINE DECOBERT ,  FENG ZHOU ,  JINHO KIM ,  XIAN LIU ,  NHAN DO

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US20200176459A1

公开(公告)日：2020-06-04

申请号：US16208150

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  JINHO KIM ,  XIAN LIU ,  SERGUEI JOURBA ,  CATHERINE DECOBERT ,  NHAN DO

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

公开(公告)号：US20170103991A1

公开(公告)日：2017-04-13

申请号：US15264457

申请日：2016-09-13

Applicant: Silicon Storage Technology, Inc.

Inventor： JINHO KIM ,  CHIEN-SHENG SU ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO ,  PRATEEP TUNTASOOD ,  PARVIZ GHAZAVI

IPC: H01L27/115

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.