公开(公告)号：US6147369A

公开(公告)日：2000-11-14

申请号：US223652

申请日：1998-12-30

申请人： Wei-Fan Chen ,  Fu-Chien Chiu ,  Ta-Lee Yu

发明人： Wei-Fan Chen ,  Fu-Chien Chiu ,  Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L23/62 ,  H01L29/00 ,  H01L31/111

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An electrostatic discharge protective circuit of the invention includes a silicon controller rectifier (SCR) and a current diverter. The current diverter is used to bypass an initial low current thereby to prevent the SCR from being triggered by the low current. Thus, a trigger current required to activate the SCR can be greatly increased thereby to maintain an internal circuit at a normal operating state.

摘要翻译： 本发明的静电放电保护电路包括硅控整流器（SCR）和电流分流器。 电流分流器用于绕过初始低电流，从而防止SCR被低电流触发。 因此，可以大大增加激活SCR所需的触发电流，从而保持内部电路处于正常工作状态。

公开(公告)号：US6014298A

公开(公告)日：2000-01-11

申请号：US67860

申请日：1998-04-27

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H02H9/04 ,  H02H9/00

CPC分类号： H02H9/046

摘要： The protection circuit of the invention connects in series with an internal circuit between a first power source and a second power source. The protection circuit includes a switch which is connected with the internal circuit and one of the first power source and a second power source; and a delay circuit which connects with the switch. The switch which is controlled by the delay circuit is closed for providing a voltage to the internal circuit in normal operation mode, and is opened when an electrostatic stress occurs.

摘要翻译： 本发明的保护电路与第一电源和第二电源之间的内部电路串联。 保护电路包括与内部电路和第一电源和第二电源之一连接的开关; 以及与开关连接的延迟电路。 由延迟电路控制的开关被关闭以在正常操作模式下向内部电路提供电压，并且当发生静电应力时打开。

公开(公告)号：US5912494A

公开(公告)日：1999-06-15

申请号：US630735

申请日：1996-04-02

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0266 ,  H01L2924/0002

摘要： An ESD protected structure and method of its fabrication are disclosed. A heavily doped polycrystalline silicon region of a first conductivity type is disposed on a substrate surface and is connected to a power supply voltage. A lightly doped region, of the first conductivity type, is disposed below the substrate surface and below the polycrystalline silicon region. A first heavily doped region, of the first conductivity type, of a first MOS device is disposed below the substrate surface, and contained entirely within the lightly doped region. A second heavily doped region, of the first conductivity type, of a second MOS device, is disposed below the substrate surface, and separated from the first region by a portion of the lightly doped region and a second conductivity type doped portion of the substrate. The separation of the first and second regions by a portion of the lightly doped region increases a turn-on voltage of a parasitic bipolar junction device that includes the first and second regions, the portion of the lightly doped region and the second conductivity type doped portion of the substrate. The increase in turn on voltage, in turn, tends to prevent the bipolar junction device from turning on, during an ESD event, before an ESD protection device that protects the structure from ESD events which occur within the power supply voltage. According to the fabrication process, the heavily doped polycrystalline silicon region is formed on the substrate surface and impurities are thermally diffused therefrom below the substrate surface to form the lightly doped region.

公开(公告)号：US5838050A

公开(公告)日：1998-11-17

申请号：US932010

申请日：1997-09-17

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chien-Chang Huang ,  Chau-Neng Wu ,  Ta-Lee Yu

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chien-Chang Huang ,  Chau-Neng Wu ,  Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L27/72

CPC分类号： H01L27/0251 ,  H01L27/092

摘要： A CMOS device containing a plurality of hexagon cells over a semiconductor substrate is disclosed. Each hexagon cell includes a hexagonal ring gate, a drain diffusion region and a source diffusion region. The hexagonal ring gate is made of conducting materials and a dielectric layer over the substrate, therefore defining a channel region in the substrate between the gate and the substrate. The entire drain diffusion region in the substrate is enclosed by the hexagonal ring gate. The source diffusion region surrounds the hexagonal ring gate in the substrate. Each hexagon cell further provides a drain contact in the center of the drain diffusion region. A plurality of source contacts are arranged around the ring gate over the substrate. The hexagon cells of a unique hexagon device are surrounded by a first guard ring and a second guard ring. The hexagon device can be used as a CMOS output buffer or input ESD protection circuit to reduce the layout area of an integrated circuit.

摘要翻译： 公开了一种在半导体衬底上包含多个六边形单元的CMOS器件。 每个六边形单元包括六边形环形栅极，漏极扩散区域和源极扩散区域。 六角环形栅极由导电材料和介质层构成，因此在栅极和衬底之间在衬底中限定沟道区。 衬底中的整个漏极扩散区域被六边形环形栅极包围。 源极扩散区域围绕衬底中的六角形环形栅极。 每个六边形单元还在漏极扩散区域的中心处提供漏极接触。 在环形栅极周围多个源极触点布置在衬底上。 独特的六边形装置的六边形单元被第一保护环和第二保护环包围。 六边形器件可用作CMOS输出缓冲器或输入ESD保护电路，以减少集成电路的布局面积。

公开(公告)号：US5714784A

公开(公告)日：1998-02-03

申请号：US545286

申请日：1995-10-19

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chien-Chang Huang ,  Chau-Neng Wu ,  Ta-Lee Yu

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chien-Chang Huang ,  Chau-Neng Wu ,  Ta-Lee Yu

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L23/62 ,  H01L29/76

CPC分类号： H01L29/1087 ,  H01L27/0251 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/4238 ,  H01L2924/0002

摘要： The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.

摘要翻译： 本发明是电子器件，特别是MOS晶体管。 使用方形布局样式来实现MOS器件。 通过使用当前的布局方式，输出缓冲器的输出驱动/吸收能力以及输出缓冲器或输入ESD保护电路中的NMOS和PMOS器件的ESD保护能力在较小的布局区域内得到显着改善。 通过这种正方形布局，输出节点处的漏极扩散面积和漏极到体积寄生电容都减小了。 使用本布局样式的设备可以组装成更大的矩形（或方形）和类似功能的设备。 因此，目前的方形布局样式对于亚微米CMOS VLSI / ULSI在高密度和高速应用中非常有吸引力。

公开(公告)号：US5712753A

公开(公告)日：1998-01-27

申请号：US643355

申请日：1996-05-06

申请人： Yang-Sen Yeh ,  Ta-Lee Yu ,  Kow-Liang Wen

发明人： Yang-Sen Yeh ,  Ta-Lee Yu ,  Kow-Liang Wen

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L27/0259

摘要： An integrated circuit package includes a semiconductor chip, bonding pads on the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin. The non-wired pin is connected electrically to an adjacent one of the wired pins to prevent electrostatic discharge failure in the integrated circuit package due to electrostatic discharge stressing of the non-wired pin.

摘要翻译： 集成电路封装包括半导体芯片，半导体芯片上的接合焊盘，分别引线键合到接合焊盘的多个有线引脚和至少一个非有线引脚。 无线引脚电连接到相邻的一个有线引脚，以防止由于非接线引脚的静电放电引起的集成电路封装中的静电放电故障。

公开(公告)号：US20120115282A1

公开(公告)日：2012-05-10

申请号：US13291093

申请日：2011-11-07

申请人： CHI KANG LIU ,  Ta Lee Yu ,  Quan Li

发明人： CHI KANG LIU ,  Ta Lee Yu ,  Quan Li

IPC分类号： H01L21/331

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

摘要翻译： 一种制造半导体器件的方法包括提供第一导电类型的衬底，并具有表面区域，形成第二导电类型的阱区域并且在衬底中具有第一深度，添加覆盖在表面区域上的栅极电介质层， 添加覆盖所述栅介质层的栅极层，形成所述第一导电类型的第一LDD区，并且在所述阱区内具有第二深度，在所述第一LDD区内形成所述第二导电类型的发射极区，以及形成第二LDD 具有阱区的第一导电类型的区域，沟道区域分离第一和第二LDD区域。 该方法还包括在第二LDD区域内形成具有第一导电类型的源极区域，并且将耦合到漏极和发射极区域的输出焊盘相加。

公开(公告)号：US20100027172A1

公开(公告)日：2010-02-04

申请号：US12483195

申请日：2009-06-11

申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

IPC分类号： H02H9/04 ,  H01L29/739 ,  H01L21/331

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

公开(公告)号：US07239186B2

公开(公告)日：2007-07-03

申请号：US11262505

申请日：2005-10-28

申请人： Ta-Lee Yu ,  Lei Wang ,  Li An Da

发明人： Ta-Lee Yu ,  Lei Wang ,  Li An Da

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K19/003

摘要： A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

摘要翻译： 一种用于控制输入/输出驱动器的系统和方法。 该系统包括被配置为接收第一电源电压和第二电源电压并产生控制信号的控制系统，以及包括第一门，第一终端和第二终端的第一晶体管。 第一栅极被配置为接收控制信号，并且第一端子被配置为接收第一电源电压。 另外，该系统包括包括第二栅极，第三端子和第四端子的第二晶体管，并且第二栅极耦合到第二端子。 此外，该系统包括包括第三栅极，第五端子和第六端子的第三晶体管，并且第三栅极被配置为接收控制信号。 此外，该系统包括耦合到第四端子和第五端子的输入/输出焊盘。

公开(公告)号：US06888201B2

公开(公告)日：2005-05-03

申请号：US10790919

申请日：2004-03-02

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L21/331 ,  H01L23/62 ,  H01L27/02 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L29/732 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/11 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7322 ,  H01L27/0259

摘要： The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations in the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.

摘要翻译： 本发明描述了具有改进的ESD保护和弹性的集成电路半导体器件的ESD保护器件的制造和结构。 垂直双极性npn晶体管构成保护器件的基础。 为了处理ESD事件的大电流要求，双极晶体管具有以npn双极阵列形成的多个基极和发射极元件。 为了确保阵列的多个元件的导通，发射器指状物连续地或连续地连接着独特的发射器设计布局。 连续的发射器设计为器件提供了改进的发射极连接，使使用分离的发射极手指时可能发生的任何不平衡最小化，并提高了多个发射极 - 基极元件同时导通的能力。 发射极包含在集电极元件的占地面积内，并且能够容纳器件尺寸，从而最大程度地降低了高速电路设计中重要的器件电容特性。 本发明的其它实施例使用公共连续发射极导体的结构的变化以及不同的基底导体结构布局。