公开(公告)号：US07970960B2

公开(公告)日：2011-06-28

申请号：US12262412

申请日：2008-10-31

申请人： Ik-Jae Chun ,  Jung-Hee Suk ,  Tae-Moon Roh ,  Jong-Dae Kim

发明人： Ik-Jae Chun ,  Jung-Hee Suk ,  Tae-Moon Roh ,  Jong-Dae Kim

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Provided is a direct memory access (DMA) controller. The DMA controller includes a plurality of channel groups and a channel group controller. Each of the channel groups has a plurality of DMA channels, and the channel group controller controls enablement of the DMA channels in units of channel groups. Herein, the channel group controller enables the DMA channels of at least one of the channel groups in data transmission.

摘要翻译： 提供了直接存储器访问（DMA）控制器。 DMA控制器包括多个信道组和信道组控制器。 每个通道组具有多个DMA通道，并且通道组控制器控制以通道组为单位的DMA通道的使能。 这里，信道组控制器使数据传输中的至少一个信道组的DMA信道成为可能。

公开(公告)号：US20110142345A1

公开(公告)日：2011-06-16

申请号：US12783180

申请日：2010-05-19

申请人： Sang Hun Yoon ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Sang Hun Yoon ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： G06K9/46

CPC分类号： G06K9/4614

摘要： Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1st to nth order gradients of the x- and y-axis of an input image, and the input image is correctly classified as a true or false image using, in stages, the extracted features of the input image, multiple threshold values for a true image and multiple threshold values for a false image. Accordingly, the apparatus and method achieve a high recognition rate by performing a small amount of computation. Consequently, it is possible to rapidly and correctly recognize an image, enabling real-time image recognition.

摘要翻译： 提供了一种用于识别图像的装置和方法。 在用于识别图像的装置和方法中，可以通过输入图像的x轴和y轴的第1至n阶梯度的Haar样滤波器提取各种特征，并且输入图像被正确地分类为真 或分别使用输入图像的提取特征，用于真实图像的多个阈值和用于假图像的多个阈值的假图像。 因此，该装置和方法通过执行少量的计算来实现高识别率。 因此，可以快速且正确地识别图像，从而实现图像识别。

公开(公告)号：US20110022647A1

公开(公告)日：2011-01-27

申请号：US12843550

申请日：2010-07-26

申请人： Chun Gi LYUH ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Chun Gi LYUH ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： G06F7/485

CPC分类号： G06F7/544

摘要： Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.

摘要翻译： 提供了一种用于计算能够使用加法器有效地执行绝对差的绝对差的装置。 用于计算绝对差的装置包括比较器，比较器比较两个整数的值，第一和第二选择器，每个选择器根据比较器的比较结果选择和输出两个整数中的一个;逆变器，补偿由第二选择器选择的结果值; 和加法器将由第一选择器选择的结果值相加，由逆变器补充的值，以及1。

公开(公告)号：US07769981B2

公开(公告)日：2010-08-03

申请号：US12045844

申请日：2008-03-11

申请人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

发明人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

IPC分类号： G06F15/80

CPC分类号： G06F15/8007

摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

公开(公告)号：US07759737B2

公开(公告)日：2010-07-20

申请号：US11924903

申请日：2007-10-26

申请人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.

摘要翻译： 提供了一种双重结构的FinFET及其制造方法。 FinFET包括：下部器件，包括形成在衬底上的下硅层和垂直形成在衬底上的栅电极; 上部器件，包括形成在下部器件上的上硅层和垂直形成的栅电极; 以及顺序地形成在下硅层和上硅层之间的第一固体源材料层，固体源材料层间绝缘层和第二固体源材料层。 因此，可以提供FinFET，其增强电路的集成密度，抑制由于使用固相材料层的离子注入引起的薄膜损伤，并且通过简单且低成本的工艺具有稳定的特性。 此外，可以提高上部器件的迁移率以增强上部器件的电流驱动能力，可以通过掩埋氧化物层实现隔离，以减少由于场氧化物层引起的影响，并且可以实现升高的源极和漏极以减少串联 源极和漏极的电阻分量以增加电流驱动能力。

公开(公告)号：US07709330B2

公开(公告)日：2010-05-04

申请号：US11745574

申请日：2007-05-08

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减少导致跨导增益（Gm），结果是热电子效应被抑制，并且器件的可靠性增强。

公开(公告)号：US07461235B2

公开(公告)日：2008-12-02

申请号：US11144703

申请日：2005-06-06

申请人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Sang Heung Lee ,  Jong Dae Kim

发明人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Sang Heung Lee ,  Jong Dae Kim

IPC分类号： G06F15/76 ,  G06F1/32

CPC分类号： G06F9/3885 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/30141 ,  G06F9/30156 ,  G06F9/3822 ,  G06F9/3824 ,  Y02D10/171

摘要： Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.

摘要翻译： 提供了一种用于高能效的并行数据路径架构。 在该架构中，处理单元的多个并行处理单元和多个功能单元由指令控制并且并行处理以提高性能。 此外，由于只需要必要的处理单元和功能单元，所以功耗降低以提高能量效率。 此外，通过使用简单的指令格式，可以将硬件编程为用于高能量效率的并行数据路径体系结构，其既能满足优异性能又具有低功耗，从而提高硬件灵活性。

公开(公告)号：US07420403B2

公开(公告)日：2008-09-02

申请号：US11520165

申请日：2006-09-13

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Dae Woo Lee

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Dae Woo Lee

IPC分类号： H03K3/00

CPC分类号： H03K19/0013 ,  H03K3/356156 ,  H03K3/356182

摘要： A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit is presented that uses both low and high threshold inverters. The multi-threshold latch circuit includes: a low threshold forward clock inverter inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a high threshold backward clock inverter forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.

摘要翻译： 提出了一种高可靠性，多阈值互补金属氧化物半导体（CMOS）锁存电路，其使用低和高阈值逆变器。 多阈值锁存电路包括：当门限处于第一逻辑状态时，低阈值正向时钟反相器反相输入端逻辑状态并将反相逻辑状态施加到输出端逻辑状态; 以及高阈值反向时钟反相器，与正向时钟反相器一起形成圆形锁存结构，并且在时钟处于第二逻辑状态时反相输入端逻辑状态并将反相逻辑状态应用于输出逻辑状态。

公开(公告)号：US07335945B2

公开(公告)日：2008-02-26

申请号：US11012695

申请日：2004-12-16

申请人： Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

IPC分类号： H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78645

摘要： Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.

摘要翻译： 提供一种多栅极MOS晶体管及其制造方法。 垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。 因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

公开(公告)号：US07332774B2

公开(公告)日：2008-02-19

申请号：US11727268

申请日：2007-03-26

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66818

摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

摘要翻译： 提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域 通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。 由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被 栅电极。 此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。