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公开(公告)号：US20240407273A1
公开(公告)日：2024-12-05
申请号：US18218602
申请日：2023-07-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Hsiang-Hung Peng , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.
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公开(公告)号：US20240404587A1
公开(公告)日：2024-12-05
申请号：US18218025
申请日：2023-07-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Li-Ping Huang , Chun-Yen Tseng
IPC: G11C11/412 , G11C5/06
Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.
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公开(公告)号：US12161050B2
公开(公告)日：2024-12-03
申请号：US17944242
申请日：2022-09-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ching-Hua Hsu , Chen-Yi Weng , Jing-Yin Jhang , Po-Kai Hsu
Abstract: The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.
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公开(公告)号：US20240397838A1
公开(公告)日：2024-11-28
申请号：US18795158
申请日：2024-08-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu
Abstract: A semiconductor memory device includes a substrate; a first dielectric layer on the substrate; and bottom electrodes on the first dielectric layer. The bottom electrodes are arranged equidistantly in a first direction and extend along a second direction. A second dielectric layer is disposed on the first dielectric layer. Top electrodes are disposed in the second dielectric layer and arranged at intervals along the second direction. Each top electrode includes a lower portion located around each bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrodes and around the tapered upper portion. A resistive-switching layer is disposed between a sidewall of each bottom electrode and a sidewall of the lower portion and between the third dielectric layer and a sidewall of the tapered upper portion. An air gap is disposed in the third dielectric layer.
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公开(公告)号：US20240397833A1
公开(公告)日：2024-11-28
申请号：US18791412
申请日：2024-07-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chun-Hsien Lin
Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.
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Patent Agency Ranking
公开(公告)号：US20240395929A1
公开(公告)日：2024-11-28
申请号：US18337396
申请日：2023-06-19
Applicant: United Microelectronics Corp.
Inventor： Chen-Yuan Lin , Yu-Cheng Lo , Tzu-Yun Chang
IPC: H01L29/78 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66
Abstract: A semiconductor device includes a gate structure, a first doped region, a second doped region, an isolation structure, an insulating layer and a field plate. The gate structure is located on a substrate. The first doped region and the second doped region are located at two sides of the gate structure. The isolation structure is located in the substrate between the first doped region and the second doped region, and is separated from the gate structure by a non-zero distance. The insulating layer extends continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure. The field plate is located on the insulating layer and has the same potential as the gate structure.
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公开(公告)号：US20240395834A1
公开(公告)日：2024-11-28
申请号：US18795147
申请日：2024-08-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Zhaoyao Zhan , Qianwei DING , Xiaohong JIANG , Ching Hwa TEY
IPC: H01L27/146
Abstract: A photosensitive device includes an integrated circuit structure and a plurality of photodiodes disposed on the integrated circuit structure. The photodiodes respectively includes a first material layer and a second material layer overlapping on the first material layer and extending beyond the first material layer to directly contact a surface of the integrated circuit structure. The first material layer and the second material layer are made of two-dimensional semiconductor materials.
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公开(公告)号：US20240393676A1
公开(公告)日：2024-11-28
申请号：US18334382
申请日：2023-06-14
Applicant: United Microelectronics Corp.
Inventor： Ming-Hsien Kuo , Chih-Hsien Tang , Song-Yi Lin
IPC: G03F1/70 , G06F30/398
Abstract: A design method of a photomask structure including the following steps is provided. A layout pattern is provided. The layout pattern includes first to third basic patterns. The second basic pattern is located between the first and third basic patterns and connected to the first and third basic patterns. There is a first jog portion between the first and second basic patterns, there is a second jog portion between the second and third basic patterns, and the first and second jog portions are located at two opposite sides of the layout pattern. The first and second jog portions are moved to align the first and second jog portions with each other and to eliminate the second basic pattern, wherein a first area change amount produced by moving the first jog portion is equal to a second area change amount produced by moving the second jog portion.
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公开(公告)号：US12156487B2
公开(公告)日：2024-11-26
申请号：US18382055
申请日：2023-10-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Hsu , Wang Xiang , Shen-De Wang
Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.
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公开(公告)号：US12150315B2
公开(公告)日：2024-11-19
申请号：US18395649
申请日：2023-12-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
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