公开(公告)号：US20050127417A1

公开(公告)日：2005-06-16

申请号：US10730892

申请日：2003-12-10

申请人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

发明人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/314 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/94

CPC分类号： H01L21/31111 ,  H01L21/28194 ,  H01L21/31105 ,  H01L21/31122 ,  H01L29/517

摘要： A method for making an ultrathin high-k gate dielectric for use in a field effect transistor is provided. The method involves depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching. In addition to the above, the present invention relates to an ultrathin high-k gate dielectric made for use in a field-effect transistor made by the above method.

摘要翻译： 提供一种用于制造用于场效应晶体管的超薄高k栅极电介质的方法。 该方法包括在衬底上沉积高k栅极电介质材料，并通过对高k栅极电介质材料进行稀化处理来形成超薄高介电常数。 用于稀薄高k介电材料的方法可以包括湿法蚀刻，干法蚀刻（包括气体簇离子束（GCIB）处理）和混合损伤/湿式蚀刻的任何数量的工艺中的至少一种。 除了上述之外，本发明涉及一种用于通过上述方法制造的场效应晶体管的超薄高k栅极电介质。

公开(公告)号：US20050118757A1

公开(公告)日：2005-06-02

申请号：US10725851

申请日：2003-12-02

申请人： Cyril Cabral ,  Jakub Kedzierski ,  Victor Ku ,  Christian Lavoie ,  Vijay Narayanan ,  An Steegen

发明人： Cyril Cabral ,  Jakub Kedzierski ,  Victor Ku ,  Christian Lavoie ,  Vijay Narayanan ,  An Steegen

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823835

摘要： A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in fabricating a CMOS structure containing silicide contacts and silicide gate metals.

摘要翻译： 提供了允许使用自对准工艺（自对准硅化物）以及一个或多个光刻步骤并入硅化物触点（S / D和栅极）和金属硅化物栅极的CMOS硅化物金属集成方案。 本发明的集成方案最小化了制造包含硅化物触点和硅化物栅极金属的CMOS结构所涉及的复杂性和成本。

公开(公告)号：US09252229B2

公开(公告)日：2016-02-02

申请号：US13605267

申请日：2012-09-06

申请人： Takashi Ando ,  Vijay Narayanan

发明人： Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/02 ,  H01L29/49 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4966 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/66606 ,  H01L29/7833

摘要： A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer.

摘要翻译： 形成晶体管器件的方法包括在半导体衬底上形成对应于衬底中形成的掺杂源极和漏极区域之间的界面层; 在界面层上形成高介电常数（高k）层，高k层的介电常数大于约7.5; 在高k层上形成掺杂金属层; 进行热处理以使掺杂的金属层清除从界面层扩散的氧原子，使得界面层的最终厚度小于约5埃（）; 以及在高k电介质层上形成金属栅极材料。

公开(公告)号：US08785995B2

公开(公告)日：2014-07-22

申请号：US13108340

申请日：2011-05-16

申请人： Catherine A. Dubourdieu ,  David J. Frank ,  Martin M. Frank ,  Vijay Narayanan ,  Paul M. Solomon ,  Thomas N. Theis

发明人： Catherine A. Dubourdieu ,  David J. Frank ,  Martin M. Frank ,  Vijay Narayanan ,  Paul M. Solomon ,  Thomas N. Theis

IPC分类号： H01L21/02 ,  H01L21/00

CPC分类号： H01L29/4232 ,  H01L29/42316 ,  H01L29/812

摘要： Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”). The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.

摘要翻译： 提供了铁电半导体开关器件，包括具有栅极叠层结构的场效应晶体管（FET）器件，栅极叠层结构形成有设置在栅极接触和薄导电层（“量子传导层”）之间的铁电层。 栅极接触和铁电层用于调制薄导电层的有效功函数。 具有调制功函数的薄导电层耦合到半导体沟道层，以调制通过半导体的电流，并实现陡峭的子阈值斜率。

公开(公告)号：US08716088B2

公开(公告)日：2014-05-06

申请号：US13534573

申请日：2012-06-27

申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

公开(公告)号：US20140001573A1

公开(公告)日：2014-01-02

申请号：US13547772

申请日：2012-07-12

申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC分类号： H01L29/78

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

摘要翻译： 提供半导体结构。 该结构包括半导体材料的半导体衬底和具有介电常数大于硅的介电常数介电层的栅极电介质。 栅极电介质位于半导体衬底上。 栅电极邻接栅极电介质。 栅电极包括邻接栅电介质的下金属层，邻接下金属层的扫除金属层，与清扫金属层邻接的上金属层和邻接上金属层的硅层。 清除金属层响应于退火而在上金属层和硅层之间的界面处减少氧化层。

公开(公告)号：US20140001516A1

公开(公告)日：2014-01-02

申请号：US13614962

申请日：2012-09-13

申请人： Takashi ANDO ,  Martin M. FRANK ,  Vijay NARAYANAN

发明人： Takashi ANDO ,  Martin M. FRANK ,  Vijay NARAYANAN

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L21/823462 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/82345 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66522

摘要： A semiconductor structure includes a high mobility semiconductor, an interfacial oxide layer, a high dielectric constant (high-k) layer, a stack, a gate electrode, and a gate dielectric. The stack comprises a lower metal layer, a scavenging metal layer comprising a scavenging metal, and an upper metal layer formed on the scavenging metal layer. A Gibbs free energy change of a chemical reaction, in which an atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer combines with a metal oxide material comprising the scavenging metal and oxygen to form the scavenging metal in elemental form and oxide of the atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer, is positive.

摘要翻译： 半导体结构包括高迁移率半导体，界面氧化物层，高介电常数（高k）层，堆叠，栅极电极和栅极电介质。 堆叠包括下金属层，包含清除金属的清除金属层和形成在扫气金属层上的上金属层。 化学反应的吉布斯自由能变化，其中构成直接与界面氧化物层接触的高迁移率半导体层的原子与包含清除金属和氧的金属氧化物材料结合，以形成元素形式的清除金属和氧化物 构成与界面氧化物层直接接触的高迁移率半导体层的原子为正。

公开(公告)号：US08569844B2

公开(公告)日：2013-10-29

申请号：US12211649

申请日：2008-09-16

申请人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L31/119

CPC分类号： H01L21/823857 ,  H01L21/823878 ,  H01L21/84

摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。 根据本发明，nFET和pFET都包括至少单个栅极金属，并且nFET栅极堆叠被设计为具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质 堆没有净正电荷。 特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。 在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质 。

公开(公告)号：US08564074B2

公开(公告)日：2013-10-22

申请号：US13306621

申请日：2011-11-29

申请人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

发明人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

IPC分类号： H01L31/119

CPC分类号： H01L21/28247 ,  H01L21/28123 ,  H01L21/76224

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

摘要翻译： 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括：高K电介质区域; 阻挡区域，其设置在所述高K电介质区域的至少一个表面上，并适于响应于暴露于氧气而形成氧化层; 以及设置在阻挡区域上的富氧区域，使得阻挡区域介于富氧区域和高K电介质区域之间。

公开(公告)号：US08500961B2

公开(公告)日：2013-08-06

申请号：US13201743

申请日：2010-02-15

申请人： Guenter Forster ,  Vijay Narayanan Swaminathan

发明人： Guenter Forster ,  Vijay Narayanan Swaminathan

IPC分类号： B01D3/34

CPC分类号： C07D233/54

摘要： Method of distilling mixtures comprising salts having a melting point of less than 200° C. at 1 bar (ionic liquids), wherein the mixtures additionally comprise an organic compound (called distillation aid below) which is not ionic has a molecular weight of less than 5000 has a boiling point which is at least 5° C. higher compared with the ionic mixtures included in the mixture.

摘要翻译： 在1巴（离子液体）下蒸馏出具有熔点小于200℃的盐的混合物的方法，其中所述混合物另外包含不离子的有机化合物（称为蒸馏助剂），其分子量小于 5000的沸点比混合物中包含的离子混合物高至少5℃。